Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	683939831	6251343	0	0
wdog_bark_thold_rd_A	683939831	118043	0	0
wdog_bite_thold_rd_A	683939831	104057	0	0
wdog_ctrl_rd_A	683939831	102623	0	0
wdog_regwen_rd_A	683939831	119354	0	0
wkup_ctrl_rd_A	683939831	102487	0	0
wkup_thold_hi_rd_A	683939831	117519	0	0
wkup_thold_lo_rd_A	683939831	101698	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683939831	6251343	0	0
T2	199438	40752	0	0
T3	6773	0	0	0
T4	38908	0	0	0
T5	547387	212183	0	0
T6	141228	0	0	0
T7	493296	114163	0	0
T8	459374	122585	0	0
T9	227235	0	0	0
T10	330788	90146	0	0
T11	415266	57474	0	0
T28	0	96809	0	0
T35	0	120317	0	0
T36	0	79897	0	0
T37	0	317735	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683939831	118043	0	0
T2	199438	4294	0	0
T3	6773	0	0	0
T4	38908	0	0	0
T5	547387	0	0	0
T6	141228	0	0	0
T7	493296	12146	0	0
T8	459374	0	0	0
T9	227235	0	0	0
T10	330788	0	0	0
T11	415266	2889	0	0
T36	0	7806	0	0
T46	0	13700	0	0
T95	0	10121	0	0
T96	0	2319	0	0
T97	0	16991	0	0
T98	0	9978	0	0
T99	0	6419	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683939831	104057	0	0
T2	199438	3478	0	0
T3	6773	0	0	0
T4	38908	0	0	0
T5	547387	0	0	0
T6	141228	0	0	0
T7	493296	10979	0	0
T8	459374	0	0	0
T9	227235	0	0	0
T10	330788	0	0	0
T11	415266	2489	0	0
T36	0	7192	0	0
T46	0	12406	0	0
T95	0	8904	0	0
T96	0	2037	0	0
T97	0	14652	0	0
T98	0	8845	0	0
T99	0	5402	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683939831	102623	0	0
T2	199438	3470	0	0
T3	6773	0	0	0
T4	38908	0	0	0
T5	547387	0	0	0
T6	141228	0	0	0
T7	493296	10662	0	0
T8	459374	0	0	0
T9	227235	0	0	0
T10	330788	0	0	0
T11	415266	2605	0	0
T36	0	6953	0	0
T46	0	12158	0	0
T95	0	8873	0	0
T96	0	2169	0	0
T97	0	14992	0	0
T98	0	9104	0	0
T99	0	5112	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683939831	119354	0	0
T2	199438	4384	0	0
T3	6773	0	0	0
T4	38908	0	0	0
T5	547387	0	0	0
T6	141228	0	0	0
T7	493296	12150	0	0
T8	459374	0	0	0
T9	227235	0	0	0
T10	330788	0	0	0
T11	415266	2964	0	0
T36	0	8129	0	0
T46	0	14314	0	0
T95	0	10497	0	0
T96	0	2425	0	0
T97	0	16865	0	0
T98	0	9936	0	0
T99	0	6269	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683939831	102487	0	0
T2	199438	3441	0	0
T3	6773	0	0	0
T4	38908	0	0	0
T5	547387	0	0	0
T6	141228	0	0	0
T7	493296	10343	0	0
T8	459374	0	0	0
T9	227235	0	0	0
T10	330788	0	0	0
T11	415266	2693	0	0
T36	0	6928	0	0
T46	0	12200	0	0
T95	0	8867	0	0
T96	0	2094	0	0
T97	0	14536	0	0
T98	0	8598	0	0
T99	0	5476	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683939831	117519	0	0
T2	199438	4154	0	0
T3	6773	0	0	0
T4	38908	0	0	0
T5	547387	0	0	0
T6	141228	0	0	0
T7	493296	12055	0	0
T8	459374	0	0	0
T9	227235	0	0	0
T10	330788	0	0	0
T11	415266	3046	0	0
T36	0	7613	0	0
T46	0	13659	0	0
T95	0	10329	0	0
T96	0	2360	0	0
T97	0	17618	0	0
T98	0	9925	0	0
T99	0	6057	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	683939831	101698	0	0
T2	199438	3600	0	0
T3	6773	0	0	0
T4	38908	0	0	0
T5	547387	0	0	0
T6	141228	0	0	0
T7	493296	10258	0	0
T8	459374	0	0	0
T9	227235	0	0	0
T10	330788	0	0	0
T11	415266	2486	0	0
T36	0	7323	0	0
T46	0	11744	0	0
T95	0	8587	0	0
T96	0	2169	0	0
T97	0	14753	0	0
T98	0	8752	0	0
T99	0	5238	0	0