Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342717	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4231534	1		T1	234		T2	14		T3	16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1126491	1		T1	26		T2	1		T3	1
values[0x0]	1617753	1		T1	150		T2	11		T3	14
values[0x1]	1830007	1		T1	137		T2	7		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153484	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4420767	1		T1	251		T2	14		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19512	1		T10	1		T13	665		T15	2
valid_sources[0x01]	17536	1		T13	615		T15	3		T16	1
valid_sources[0x02]	19350	1		T8	1		T10	1		T13	688
valid_sources[0x03]	17049	1		T10	1		T13	662		T17	52
valid_sources[0x04]	18020	1		T13	659		T16	3		T17	92
valid_sources[0x05]	18588	1		T13	684		T15	2		T16	1
valid_sources[0x06]	20802	1		T6	2		T10	3		T13	645
valid_sources[0x07]	17135	1		T13	691		T15	1		T16	1
valid_sources[0x08]	18331	1		T8	1		T13	681		T15	1
valid_sources[0x09]	16655	1		T8	1		T13	640		T15	2
valid_sources[0x0a]	18755	1		T2	5		T8	4		T13	631
valid_sources[0x0b]	17192	1		T4	1		T10	1		T13	680
valid_sources[0x0c]	18680	1		T10	1		T13	710		T15	2
valid_sources[0x0d]	19553	1		T6	1		T10	1		T13	599
valid_sources[0x0e]	17724	1		T8	2		T13	647		T16	1
valid_sources[0x0f]	16894	1		T10	3		T13	681		T15	1
valid_sources[0x10]	17174	1		T13	699		T15	1		T16	1
valid_sources[0x11]	16858	1		T10	1		T12	1		T13	673
valid_sources[0x12]	18261	1		T8	2		T10	1		T13	682
valid_sources[0x13]	18356	1		T8	5		T10	1		T12	1
valid_sources[0x14]	17464	1		T10	1		T13	668		T15	2
valid_sources[0x15]	16357	1		T8	2		T13	668		T15	1
valid_sources[0x16]	16931	1		T13	597		T15	1		T16	4
valid_sources[0x17]	18093	1		T8	2		T10	3		T13	617
valid_sources[0x18]	17485	1		T13	634		T16	1		T17	93
valid_sources[0x19]	17270	1		T10	4		T13	698		T15	3
valid_sources[0x1a]	18723	1		T10	1		T13	633		T15	3
valid_sources[0x1b]	16826	1		T13	591		T15	1		T16	1
valid_sources[0x1c]	17975	1		T10	2		T13	648		T16	1
valid_sources[0x1d]	18749	1		T6	1		T10	1		T13	642
valid_sources[0x1e]	17668	1		T10	1		T13	685		T17	62
valid_sources[0x1f]	17514	1		T2	12		T12	1		T13	631
valid_sources[0x20]	17481	1		T8	3		T12	1		T13	696
valid_sources[0x21]	18024	1		T8	7		T10	1		T13	682
valid_sources[0x22]	17996	1		T9	22		T13	641		T15	2
valid_sources[0x23]	18958	1		T8	2		T10	2		T13	676
valid_sources[0x24]	16762	1		T13	671		T16	2		T17	62
valid_sources[0x25]	17350	1		T8	1		T10	2		T13	696
valid_sources[0x26]	17672	1		T10	5		T13	642		T15	2
valid_sources[0x27]	18775	1		T13	699		T15	1		T16	2
valid_sources[0x28]	16947	1		T8	3		T10	3		T13	657
valid_sources[0x29]	17957	1		T8	5		T10	2		T13	627
valid_sources[0x2a]	16572	1		T8	1		T13	654		T15	2
valid_sources[0x2b]	17366	1		T10	3		T13	598		T16	4
valid_sources[0x2c]	17212	1		T4	1		T13	664		T16	2
valid_sources[0x2d]	18722	1		T7	1		T10	1		T13	662
valid_sources[0x2e]	19341	1		T10	4		T13	660		T15	1
valid_sources[0x2f]	17053	1		T12	1		T13	668		T17	100
valid_sources[0x30]	17552	1		T10	3		T13	623		T15	1
valid_sources[0x31]	17951	1		T8	3		T13	637		T15	2
valid_sources[0x32]	18333	1		T10	1		T13	655		T15	3
valid_sources[0x33]	16497	1		T13	697		T15	1		T16	1
valid_sources[0x34]	18842	1		T8	5		T13	642		T15	3
valid_sources[0x35]	18408	1		T13	682		T16	1		T17	75
valid_sources[0x36]	17834	1		T8	2		T10	1		T13	614
valid_sources[0x37]	16536	1		T13	692		T17	68		T18	460
valid_sources[0x38]	18638	1		T13	627		T15	1		T16	1
valid_sources[0x39]	18598	1		T13	668		T17	73		T18	451
valid_sources[0x3a]	17633	1		T4	1		T6	1		T10	4
valid_sources[0x3b]	16551	1		T4	1		T13	633		T15	1
valid_sources[0x3c]	16907	1		T13	669		T15	2		T16	1
valid_sources[0x3d]	16882	1		T8	2		T10	5		T13	672
valid_sources[0x3e]	17179	1		T6	1		T13	680		T15	1
valid_sources[0x3f]	17459	1		T10	3		T13	667		T15	4
valid_sources[0x40]	17076	1		T4	1		T13	655		T15	2
valid_sources[0x41]	18734	1		T10	1		T13	705		T15	2
valid_sources[0x42]	17985	1		T4	1		T8	1		T13	659
valid_sources[0x43]	17547	1		T4	1		T13	658		T15	5
valid_sources[0x44]	16935	1		T13	618		T15	2		T16	3
valid_sources[0x45]	16432	1		T10	2		T13	667		T15	2
valid_sources[0x46]	18186	1		T4	1		T10	1		T13	640
valid_sources[0x47]	18748	1		T8	5		T13	645		T15	1
valid_sources[0x48]	17047	1		T8	1		T10	1		T13	695
valid_sources[0x49]	18224	1		T13	670		T16	1		T17	80
valid_sources[0x4a]	17463	1		T10	3		T13	685		T15	2
valid_sources[0x4b]	18277	1		T10	3		T13	626		T16	2
valid_sources[0x4c]	17599	1		T8	2		T13	649		T15	1
valid_sources[0x4d]	17246	1		T8	5		T13	655		T15	2
valid_sources[0x4e]	17689	1		T13	646		T15	2		T16	1
valid_sources[0x4f]	17630	1		T13	671		T17	61		T18	562
valid_sources[0x50]	18118	1		T10	1		T13	601		T15	1
valid_sources[0x51]	17754	1		T10	4		T13	682		T14	1
valid_sources[0x52]	18901	1		T7	4		T13	649		T17	64
valid_sources[0x53]	18275	1		T8	3		T10	3		T13	637
valid_sources[0x54]	16896	1		T8	2		T10	1		T13	651
valid_sources[0x55]	18111	1		T8	1		T13	654		T15	3
valid_sources[0x56]	18840	1		T10	1		T13	696		T15	2
valid_sources[0x57]	18580	1		T5	20		T10	1		T13	622
valid_sources[0x58]	18144	1		T13	665		T17	68		T18	521
valid_sources[0x59]	20073	1		T10	2		T12	1		T13	633
valid_sources[0x5a]	17714	1		T10	2		T13	682		T15	1
valid_sources[0x5b]	17996	1		T10	3		T13	662		T16	3
valid_sources[0x5c]	16856	1		T4	1		T10	1		T13	635
valid_sources[0x5d]	17619	1		T8	5		T13	595		T16	2
valid_sources[0x5e]	16663	1		T8	3		T13	625		T16	1
valid_sources[0x5f]	16538	1		T10	2		T13	706		T15	1
valid_sources[0x60]	19485	1		T4	1		T10	2		T13	649
valid_sources[0x61]	17235	1		T8	1		T10	3		T13	659
valid_sources[0x62]	18315	1		T13	661		T15	4		T16	3
valid_sources[0x63]	17864	1		T8	4		T10	1		T13	695
valid_sources[0x64]	17319	1		T7	4		T12	2		T13	622
valid_sources[0x65]	16159	1		T13	640		T15	1		T16	2
valid_sources[0x66]	18943	1		T6	1		T8	1		T12	1
valid_sources[0x67]	17750	1		T4	1		T10	4		T13	623
valid_sources[0x68]	17271	1		T10	2		T13	657		T15	3
valid_sources[0x69]	18426	1		T8	7		T13	683		T17	58
valid_sources[0x6a]	15972	1		T10	3		T13	682		T15	1
valid_sources[0x6b]	16361	1		T10	2		T13	667		T15	1
valid_sources[0x6c]	16523	1		T4	1		T10	7		T13	661
valid_sources[0x6d]	18836	1		T8	3		T13	644		T15	1
valid_sources[0x6e]	17846	1		T8	4		T10	1		T13	671
valid_sources[0x6f]	16871	1		T10	1		T13	623		T15	2
valid_sources[0x70]	16744	1		T10	2		T13	711		T15	2
valid_sources[0x71]	17104	1		T13	680		T14	1		T15	2
valid_sources[0x72]	17412	1		T10	1		T13	662		T15	1
valid_sources[0x73]	17759	1		T10	1		T13	721		T14	2
valid_sources[0x74]	17203	1		T13	638		T15	1		T16	1
valid_sources[0x75]	19135	1		T13	662		T15	1		T16	1
valid_sources[0x76]	18454	1		T10	2		T13	667		T15	1
valid_sources[0x77]	19250	1		T13	713		T16	2		T17	82
valid_sources[0x78]	18650	1		T10	1		T13	688		T15	1
valid_sources[0x79]	15991	1		T4	1		T8	1		T10	1
valid_sources[0x7a]	18674	1		T10	1		T13	620		T15	1
valid_sources[0x7b]	18512	1		T10	3		T13	618		T15	1
valid_sources[0x7c]	18342	1		T10	1		T13	605		T16	1
valid_sources[0x7d]	19520	1		T10	1		T13	627		T15	1
valid_sources[0x7e]	17888	1		T8	1		T10	1		T13	639
valid_sources[0x7f]	20602	1		T13	658		T16	2		T39	1
valid_sources[0x80]	18142	1		T10	1		T13	692		T16	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1055976

1

T1

15

T2

1

T4

1

values[0x0]

all_enables

biggest_size

1588686

1

T1

116

T2

8

T3

10

values[0x1]

all_enables

biggest_size

1586872

1

T1

103

T2

5

T3

6