Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	721417779	4959314	0	0
wdog_bark_thold_rd_A	721417779	152871	0	0
wdog_bite_thold_rd_A	721417779	133321	0	0
wdog_ctrl_rd_A	721417779	133419	0	0
wdog_regwen_rd_A	721417779	152408	0	0
wkup_ctrl_rd_A	721417779	132777	0	0
wkup_thold_hi_rd_A	721417779	152452	0	0
wkup_thold_lo_rd_A	721417779	132345	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	721417779	4959314	0	0
T13	824939	174934	0	0
T14	9732	0	0	0
T15	124393	0	0	0
T16	338591	0	0	0
T17	938505	19229	0	0
T18	366846	143059	0	0
T23	34895	0	0	0
T24	9675	0	0	0
T31	0	64127	0	0
T32	0	151195	0	0
T33	0	65523	0	0
T34	0	114049	0	0
T35	0	104416	0	0
T36	0	210757	0	0
T37	0	55864	0	0
T38	33456	0	0	0
T39	511037	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	721417779	152871	0	0
T13	824939	17799	0	0
T14	9732	0	0	0
T15	124393	0	0	0
T16	338591	0	0	0
T17	938505	1140	0	0
T18	366846	0	0	0
T23	34895	0	0	0
T24	9675	0	0	0
T32	0	15707	0	0
T34	0	11424	0	0
T35	0	10958	0	0
T38	33456	0	0	0
T39	511037	0	0	0
T80	0	4976	0	0
T81	0	8306	0	0
T87	0	9762	0	0
T88	0	11451	0	0
T89	0	3465	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	721417779	133321	0	0
T13	824939	16023	0	0
T14	9732	0	0	0
T15	124393	0	0	0
T16	338591	0	0	0
T17	938505	962	0	0
T18	366846	0	0	0
T23	34895	0	0	0
T24	9675	0	0	0
T32	0	13489	0	0
T34	0	10218	0	0
T35	0	9018	0	0
T38	33456	0	0	0
T39	511037	0	0	0
T80	0	4307	0	0
T81	0	6985	0	0
T87	0	8807	0	0
T88	0	10387	0	0
T89	0	2830	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	721417779	133419	0	0
T13	824939	15763	0	0
T14	9732	0	0	0
T15	124393	0	0	0
T16	338591	0	0	0
T17	938505	1006	0	0
T18	366846	0	0	0
T23	34895	0	0	0
T24	9675	0	0	0
T32	0	13663	0	0
T34	0	10139	0	0
T35	0	9108	0	0
T38	33456	0	0	0
T39	511037	0	0	0
T80	0	4248	0	0
T81	0	7316	0	0
T87	0	8678	0	0
T88	0	10249	0	0
T89	0	3163	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	721417779	152408	0	0
T13	824939	17583	0	0
T14	9732	0	0	0
T15	124393	0	0	0
T16	338591	0	0	0
T17	938505	1095	0	0
T18	366846	0	0	0
T23	34895	0	0	0
T24	9675	0	0	0
T32	0	15747	0	0
T34	0	11911	0	0
T35	0	10819	0	0
T38	33456	0	0	0
T39	511037	0	0	0
T80	0	4856	0	0
T81	0	8177	0	0
T87	0	9519	0	0
T88	0	11877	0	0
T89	0	3330	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	721417779	132777	0	0
T13	824939	15718	0	0
T14	9732	0	0	0
T15	124393	0	0	0
T16	338591	0	0	0
T17	938505	885	0	0
T18	366846	0	0	0
T23	34895	0	0	0
T24	9675	0	0	0
T32	0	13252	0	0
T34	0	10306	0	0
T35	0	9128	0	0
T38	33456	0	0	0
T39	511037	0	0	0
T80	0	3964	0	0
T81	0	7596	0	0
T87	0	8456	0	0
T88	0	10688	0	0
T89	0	2929	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	721417779	152452	0	0
T13	824939	17846	0	0
T14	9732	0	0	0
T15	124393	0	0	0
T16	338591	0	0	0
T17	938505	1030	0	0
T18	366846	0	0	0
T23	34895	0	0	0
T24	9675	0	0	0
T32	0	14406	0	0
T34	0	11501	0	0
T35	0	10750	0	0
T38	33456	0	0	0
T39	511037	0	0	0
T80	0	4591	0	0
T81	0	8439	0	0
T87	0	9937	0	0
T88	0	11830	0	0
T89	0	3490	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	721417779	132345	0	0
T13	824939	16014	0	0
T14	9732	0	0	0
T15	124393	0	0	0
T16	338591	0	0	0
T17	938505	938	0	0
T18	366846	0	0	0
T23	34895	0	0	0
T24	9675	0	0	0
T32	0	13590	0	0
T34	0	10125	0	0
T35	0	9251	0	0
T38	33456	0	0	0
T39	511037	0	0	0
T80	0	4293	0	0
T81	0	7128	0	0
T87	0	8512	0	0
T88	0	10071	0	0
T89	0	2947	0	0