Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	305964	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3728604	1		T1	281		T2	58342		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	990230	1		T1	23		T2	15452		T3	1
values[0x0]	1427887	1		T1	198		T2	22394		T3	10
values[0x1]	1616451	1		T1	166		T2	25688		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	136800	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3897768	1		T1	311		T2	61277		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15553	1		T1	2		T2	211		T5	206
valid_sources[0x01]	15629	1		T2	315		T5	187		T6	633
valid_sources[0x02]	15621	1		T1	2		T2	264		T5	190
valid_sources[0x03]	16975	1		T1	2		T2	261		T5	190
valid_sources[0x04]	15444	1		T1	2		T2	238		T5	206
valid_sources[0x05]	15553	1		T1	1		T2	232		T5	185
valid_sources[0x06]	15441	1		T1	4		T2	234		T3	2
valid_sources[0x07]	16344	1		T1	1		T2	214		T5	159
valid_sources[0x08]	15220	1		T1	4		T2	254		T5	194
valid_sources[0x09]	15868	1		T1	4		T2	312		T5	178
valid_sources[0x0a]	15326	1		T2	204		T5	138		T6	677
valid_sources[0x0b]	14569	1		T1	2		T2	246		T5	198
valid_sources[0x0c]	15687	1		T2	228		T5	185		T6	779
valid_sources[0x0d]	16652	1		T1	3		T2	231		T5	185
valid_sources[0x0e]	16055	1		T2	252		T4	1		T5	152
valid_sources[0x0f]	14530	1		T2	247		T5	150		T6	743
valid_sources[0x10]	14799	1		T1	2		T2	305		T5	162
valid_sources[0x11]	15195	1		T1	3		T2	210		T5	177
valid_sources[0x12]	15161	1		T1	5		T2	253		T5	181
valid_sources[0x13]	15475	1		T2	254		T5	177		T6	808
valid_sources[0x14]	16578	1		T2	280		T5	148		T6	603
valid_sources[0x15]	15385	1		T1	3		T2	315		T5	178
valid_sources[0x16]	15316	1		T2	210		T5	190		T6	778
valid_sources[0x17]	14950	1		T2	228		T5	192		T6	658
valid_sources[0x18]	15501	1		T1	2		T2	235		T5	178
valid_sources[0x19]	15774	1		T2	226		T5	183		T6	700
valid_sources[0x1a]	15267	1		T2	233		T5	165		T6	702
valid_sources[0x1b]	16772	1		T2	225		T5	170		T6	733
valid_sources[0x1c]	16356	1		T2	240		T5	161		T6	842
valid_sources[0x1d]	14846	1		T2	220		T4	1		T5	176
valid_sources[0x1e]	14751	1		T2	270		T5	167		T6	846
valid_sources[0x1f]	14708	1		T1	2		T2	239		T5	178
valid_sources[0x20]	15417	1		T1	1		T2	265		T5	175
valid_sources[0x21]	16364	1		T2	260		T3	4		T5	145
valid_sources[0x22]	16499	1		T1	3		T2	250		T5	160
valid_sources[0x23]	14909	1		T1	2		T2	232		T5	146
valid_sources[0x24]	15373	1		T2	279		T5	180		T6	707
valid_sources[0x25]	15725	1		T2	246		T5	188		T6	741
valid_sources[0x26]	15692	1		T2	226		T5	182		T6	695
valid_sources[0x27]	15869	1		T2	238		T5	160		T6	740
valid_sources[0x28]	16545	1		T2	268		T5	171		T6	671
valid_sources[0x29]	16807	1		T1	8		T2	314		T5	191
valid_sources[0x2a]	15936	1		T1	2		T2	253		T5	176
valid_sources[0x2b]	15453	1		T1	2		T2	218		T5	180
valid_sources[0x2c]	16942	1		T2	220		T5	184		T6	631
valid_sources[0x2d]	15707	1		T1	2		T2	250		T5	184
valid_sources[0x2e]	14851	1		T1	1		T2	267		T5	171
valid_sources[0x2f]	15059	1		T2	282		T4	3		T5	162
valid_sources[0x30]	15241	1		T2	253		T5	204		T6	562
valid_sources[0x31]	16187	1		T2	307		T5	173		T6	809
valid_sources[0x32]	14152	1		T2	257		T4	1		T5	170
valid_sources[0x33]	15174	1		T2	276		T5	168		T6	704
valid_sources[0x34]	16357	1		T1	1		T2	264		T5	163
valid_sources[0x35]	16600	1		T2	290		T5	198		T6	635
valid_sources[0x36]	15844	1		T1	4		T2	252		T5	155
valid_sources[0x37]	16640	1		T1	1		T2	285		T5	174
valid_sources[0x38]	15075	1		T2	199		T5	172		T6	592
valid_sources[0x39]	15782	1		T2	254		T5	214		T6	786
valid_sources[0x3a]	15022	1		T1	1		T2	189		T5	165
valid_sources[0x3b]	15898	1		T1	3		T2	320		T5	221
valid_sources[0x3c]	15713	1		T2	222		T3	4		T5	172
valid_sources[0x3d]	16064	1		T2	189		T4	1		T5	177
valid_sources[0x3e]	16224	1		T1	2		T2	257		T5	174
valid_sources[0x3f]	16113	1		T2	211		T5	211		T6	795
valid_sources[0x40]	15875	1		T1	4		T2	235		T5	180
valid_sources[0x41]	15212	1		T1	2		T2	266		T5	172
valid_sources[0x42]	15702	1		T2	227		T5	199		T6	659
valid_sources[0x43]	15961	1		T1	3		T2	249		T5	153
valid_sources[0x44]	15232	1		T1	3		T2	237		T5	149
valid_sources[0x45]	15216	1		T1	2		T2	225		T5	171
valid_sources[0x46]	15709	1		T1	2		T2	240		T5	195
valid_sources[0x47]	15512	1		T2	255		T5	185		T6	579
valid_sources[0x48]	14992	1		T2	210		T5	167		T6	642
valid_sources[0x49]	17152	1		T2	245		T5	186		T6	721
valid_sources[0x4a]	15147	1		T2	239		T5	168		T6	669
valid_sources[0x4b]	16530	1		T2	260		T5	169		T6	713
valid_sources[0x4c]	14959	1		T1	1		T2	236		T5	202
valid_sources[0x4d]	15338	1		T1	2		T2	243		T3	3
valid_sources[0x4e]	14957	1		T1	3		T2	217		T4	1
valid_sources[0x4f]	15976	1		T1	3		T2	223		T5	161
valid_sources[0x50]	16436	1		T1	2		T2	272		T5	201
valid_sources[0x51]	15834	1		T1	4		T2	256		T4	1
valid_sources[0x52]	15876	1		T2	192		T5	200		T6	598
valid_sources[0x53]	15996	1		T1	3		T2	231		T5	170
valid_sources[0x54]	16048	1		T2	217		T5	183		T6	769
valid_sources[0x55]	15148	1		T2	302		T4	1		T5	184
valid_sources[0x56]	15801	1		T2	245		T5	191		T6	761
valid_sources[0x57]	15345	1		T2	225		T5	204		T6	600
valid_sources[0x58]	14934	1		T2	221		T5	192		T6	618
valid_sources[0x59]	15629	1		T2	250		T5	173		T6	798
valid_sources[0x5a]	16118	1		T2	278		T5	174		T6	913
valid_sources[0x5b]	15841	1		T2	240		T5	161		T6	675
valid_sources[0x5c]	16685	1		T2	272		T5	205		T6	762
valid_sources[0x5d]	16424	1		T1	6		T2	233		T5	172
valid_sources[0x5e]	15773	1		T1	5		T2	228		T5	176
valid_sources[0x5f]	15142	1		T1	7		T2	238		T5	166
valid_sources[0x60]	14999	1		T2	272		T5	174		T6	635
valid_sources[0x61]	15085	1		T1	1		T2	227		T5	213
valid_sources[0x62]	16266	1		T2	248		T5	172		T6	656
valid_sources[0x63]	15274	1		T2	263		T5	163		T6	647
valid_sources[0x64]	16990	1		T2	261		T5	188		T6	646
valid_sources[0x65]	16362	1		T1	2		T2	259		T3	1
valid_sources[0x66]	16144	1		T1	1		T2	282		T5	160
valid_sources[0x67]	15371	1		T1	3		T2	212		T5	142
valid_sources[0x68]	15846	1		T2	264		T4	1		T5	176
valid_sources[0x69]	14971	1		T1	5		T2	245		T5	187
valid_sources[0x6a]	16078	1		T2	263		T5	197		T6	668
valid_sources[0x6b]	15527	1		T1	1		T2	246		T5	174
valid_sources[0x6c]	15987	1		T1	2		T2	254		T5	162
valid_sources[0x6d]	15884	1		T1	1		T2	232		T5	167
valid_sources[0x6e]	15161	1		T1	6		T2	233		T5	148
valid_sources[0x6f]	15820	1		T2	286		T4	1		T5	194
valid_sources[0x70]	15686	1		T1	7		T2	256		T5	148
valid_sources[0x71]	16564	1		T1	4		T2	237		T5	167
valid_sources[0x72]	16409	1		T2	280		T5	160		T6	503
valid_sources[0x73]	16233	1		T1	4		T2	236		T5	176
valid_sources[0x74]	16329	1		T1	2		T2	275		T5	196
valid_sources[0x75]	15475	1		T2	230		T5	185		T6	767
valid_sources[0x76]	16084	1		T2	254		T5	193		T6	670
valid_sources[0x77]	15482	1		T2	263		T5	174		T6	589
valid_sources[0x78]	15124	1		T2	239		T5	184		T6	501
valid_sources[0x79]	16620	1		T1	8		T2	237		T5	194
valid_sources[0x7a]	15861	1		T2	218		T4	1		T5	165
valid_sources[0x7b]	16447	1		T2	278		T4	1		T5	197
valid_sources[0x7c]	15524	1		T1	5		T2	290		T5	187
valid_sources[0x7d]	14965	1		T1	1		T2	265		T5	155
valid_sources[0x7e]	16417	1		T1	3		T2	238		T3	2
valid_sources[0x7f]	15704	1		T1	4		T2	250		T5	219
valid_sources[0x80]	15104	1		T2	300		T5	192		T6	703

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

928114

1

T1

10

T2

14493

T5

10667

values[0x0]

all_enables

biggest_size

1401812

1

T1

152

T2

21955

T3

8

values[0x1]

all_enables

biggest_size

1398678

1

T1

119

T2

21894

T3

6