Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	760155976	4398927	0	0
wdog_bark_thold_rd_A	760155976	113785	0	0
wdog_bite_thold_rd_A	760155976	96641	0	0
wdog_ctrl_rd_A	760155976	98468	0	0
wdog_regwen_rd_A	760155976	111847	0	0
wkup_ctrl_rd_A	760155976	98187	0	0
wkup_thold_hi_rd_A	760155976	110306	0	0
wkup_thold_lo_rd_A	760155976	97133	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760155976	4398927	0	0
T2	291382	72492	0	0
T3	129997	0	0	0
T4	19465	0	0	0
T5	174842	51055	0	0
T6	676804	199010	0	0
T7	143002	0	0	0
T8	40053	0	0	0
T9	890604	32664	0	0
T10	52345	0	0	0
T11	335161	125605	0	0
T24	0	189662	0	0
T29	0	28132	0	0
T39	0	135124	0	0
T40	0	111858	0	0
T41	0	119957	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760155976	113785	0	0
T40	450408	6020	0	0
T41	327553	0	0	0
T47	0	6884	0	0
T89	523759	12249	0	0
T90	0	8268	0	0
T91	0	13697	0	0
T92	0	5100	0	0
T93	0	4220	0	0
T94	0	12439	0	0
T95	0	13830	0	0
T96	0	4978	0	0
T97	26305	0	0	0
T98	23794	0	0	0
T99	149693	0	0	0
T100	15606	0	0	0
T101	405655	0	0	0
T102	334427	0	0	0
T103	14849	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760155976	96641	0	0
T40	450408	5031	0	0
T41	327553	0	0	0
T47	0	5494	0	0
T89	523759	10452	0	0
T90	0	6720	0	0
T91	0	12051	0	0
T92	0	4504	0	0
T93	0	3993	0	0
T94	0	10383	0	0
T95	0	11572	0	0
T96	0	3979	0	0
T97	26305	0	0	0
T98	23794	0	0	0
T99	149693	0	0	0
T100	15606	0	0	0
T101	405655	0	0	0
T102	334427	0	0	0
T103	14849	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760155976	98468	0	0
T40	450408	5032	0	0
T41	327553	0	0	0
T47	0	5876	0	0
T89	523759	10311	0	0
T90	0	6954	0	0
T91	0	12017	0	0
T92	0	4498	0	0
T93	0	3961	0	0
T94	0	10598	0	0
T95	0	11947	0	0
T96	0	4417	0	0
T97	26305	0	0	0
T98	23794	0	0	0
T99	149693	0	0	0
T100	15606	0	0	0
T101	405655	0	0	0
T102	334427	0	0	0
T103	14849	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760155976	111847	0	0
T40	450408	6100	0	0
T41	327553	0	0	0
T47	0	6776	0	0
T89	523759	12012	0	0
T90	0	8113	0	0
T91	0	13423	0	0
T92	0	5063	0	0
T93	0	4221	0	0
T94	0	12104	0	0
T95	0	13558	0	0
T96	0	4802	0	0
T97	26305	0	0	0
T98	23794	0	0	0
T99	149693	0	0	0
T100	15606	0	0	0
T101	405655	0	0	0
T102	334427	0	0	0
T103	14849	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760155976	98187	0	0
T40	450408	4932	0	0
T41	327553	0	0	0
T47	0	5851	0	0
T89	523759	10264	0	0
T90	0	6787	0	0
T91	0	11997	0	0
T92	0	4551	0	0
T93	0	3821	0	0
T94	0	10465	0	0
T95	0	11954	0	0
T96	0	4166	0	0
T97	26305	0	0	0
T98	23794	0	0	0
T99	149693	0	0	0
T100	15606	0	0	0
T101	405655	0	0	0
T102	334427	0	0	0
T103	14849	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760155976	110306	0	0
T40	450408	5963	0	0
T41	327553	0	0	0
T47	0	6706	0	0
T89	523759	11860	0	0
T90	0	7800	0	0
T91	0	13611	0	0
T92	0	4810	0	0
T93	0	4067	0	0
T94	0	12031	0	0
T95	0	13437	0	0
T96	0	4600	0	0
T97	26305	0	0	0
T98	23794	0	0	0
T99	149693	0	0	0
T100	15606	0	0	0
T101	405655	0	0	0
T102	334427	0	0	0
T103	14849	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760155976	97133	0	0
T40	450408	5300	0	0
T41	327553	0	0	0
T47	0	6144	0	0
T89	523759	10030	0	0
T90	0	6475	0	0
T91	0	12295	0	0
T92	0	4485	0	0
T93	0	3851	0	0
T94	0	10608	0	0
T95	0	11837	0	0
T96	0	4323	0	0
T97	26305	0	0	0
T98	23794	0	0	0
T99	149693	0	0	0
T100	15606	0	0	0
T101	405655	0	0	0
T102	334427	0	0	0
T103	14849	0	0	0