Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	371549	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4557664	1		T1	15		T2	14		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1210566	1		T1	1		T2	1		T3	1
values[0x0]	1742691	1		T1	7		T2	10		T3	10
values[0x1]	1975956	1		T1	12		T2	11		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	164896	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4764317	1		T1	16		T2	15		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19143	1		T3	2		T4	23		T7	8
valid_sources[0x01]	18599	1		T4	27		T7	1		T8	8
valid_sources[0x02]	20009	1		T4	21		T9	2		T15	433
valid_sources[0x03]	18413	1		T4	24		T6	4		T40	1
valid_sources[0x04]	19369	1		T4	25		T6	1		T7	2
valid_sources[0x05]	19324	1		T4	48		T6	2		T7	5
valid_sources[0x06]	18840	1		T4	37		T6	4		T7	1
valid_sources[0x07]	18802	1		T4	30		T6	1		T9	7
valid_sources[0x08]	19084	1		T4	16		T6	1		T24	1
valid_sources[0x09]	19475	1		T1	2		T4	42		T7	8
valid_sources[0x0a]	18375	1		T4	30		T6	2		T7	5
valid_sources[0x0b]	19399	1		T2	3		T4	26		T9	6
valid_sources[0x0c]	19224	1		T4	36		T7	2		T9	2
valid_sources[0x0d]	18682	1		T4	28		T6	1		T9	3
valid_sources[0x0e]	19979	1		T1	2		T4	28		T6	1
valid_sources[0x0f]	19547	1		T4	24		T6	5		T40	1
valid_sources[0x10]	20072	1		T4	31		T6	1		T194	1
valid_sources[0x11]	19444	1		T4	27		T40	1		T15	369
valid_sources[0x12]	19025	1		T4	46		T7	1		T24	1
valid_sources[0x13]	20211	1		T4	18		T6	1		T9	6
valid_sources[0x14]	19493	1		T1	3		T4	33		T6	5
valid_sources[0x15]	18544	1		T4	26		T6	1		T9	2
valid_sources[0x16]	19861	1		T4	27		T9	1		T24	1
valid_sources[0x17]	19156	1		T4	42		T6	3		T7	3
valid_sources[0x18]	19369	1		T4	35		T6	3		T7	1
valid_sources[0x19]	21099	1		T4	20		T7	4		T9	1
valid_sources[0x1a]	19159	1		T4	31		T9	1		T24	1
valid_sources[0x1b]	18627	1		T4	26		T9	4		T24	2
valid_sources[0x1c]	19516	1		T4	27		T6	2		T7	1
valid_sources[0x1d]	18983	1		T4	41		T7	4		T40	1
valid_sources[0x1e]	19035	1		T4	23		T6	1		T9	5
valid_sources[0x1f]	18910	1		T4	26		T6	2		T24	2
valid_sources[0x20]	18388	1		T4	21		T6	3		T8	2
valid_sources[0x21]	18915	1		T4	22		T6	1		T8	12
valid_sources[0x22]	18759	1		T4	17		T6	1		T7	1
valid_sources[0x23]	18780	1		T4	31		T6	1		T7	3
valid_sources[0x24]	18287	1		T4	22		T9	2		T24	2
valid_sources[0x25]	17829	1		T3	2		T4	20		T6	2
valid_sources[0x26]	19870	1		T4	42		T7	1		T24	1
valid_sources[0x27]	18286	1		T4	28		T6	1		T7	1
valid_sources[0x28]	19063	1		T4	29		T6	1		T7	3
valid_sources[0x29]	18029	1		T4	26		T6	2		T7	5
valid_sources[0x2a]	19057	1		T4	16		T7	1		T195	1
valid_sources[0x2b]	19274	1		T4	24		T6	1		T7	1
valid_sources[0x2c]	19016	1		T4	20		T6	4		T24	2
valid_sources[0x2d]	18813	1		T4	31		T6	5		T24	1
valid_sources[0x2e]	19495	1		T4	25		T6	1		T7	1
valid_sources[0x2f]	19460	1		T2	3		T4	23		T26	1
valid_sources[0x30]	19035	1		T4	29		T6	1		T7	1
valid_sources[0x31]	19701	1		T4	43		T7	1		T9	1
valid_sources[0x32]	18300	1		T4	33		T9	1		T40	2
valid_sources[0x33]	18520	1		T4	25		T6	4		T24	5
valid_sources[0x34]	19705	1		T2	1		T4	25		T8	5
valid_sources[0x35]	18309	1		T4	32		T6	2		T24	3
valid_sources[0x36]	19543	1		T4	21		T6	2		T7	5
valid_sources[0x37]	18601	1		T3	1		T4	25		T6	2
valid_sources[0x38]	18545	1		T4	31		T6	1		T9	3
valid_sources[0x39]	19173	1		T4	26		T6	1		T7	2
valid_sources[0x3a]	20619	1		T4	34		T6	1		T9	4
valid_sources[0x3b]	18867	1		T4	25		T6	2		T9	1
valid_sources[0x3c]	18740	1		T4	31		T6	1		T9	3
valid_sources[0x3d]	18718	1		T4	34		T6	1		T9	1
valid_sources[0x3e]	19128	1		T4	25		T6	3		T7	2
valid_sources[0x3f]	19263	1		T4	26		T6	1		T40	1
valid_sources[0x40]	18384	1		T4	32		T6	1		T7	7
valid_sources[0x41]	20113	1		T4	33		T40	1		T15	433
valid_sources[0x42]	19693	1		T4	19		T6	1		T7	1
valid_sources[0x43]	18119	1		T4	27		T40	3		T15	450
valid_sources[0x44]	18583	1		T4	30		T6	3		T9	2
valid_sources[0x45]	18393	1		T4	28		T5	2		T7	2
valid_sources[0x46]	18097	1		T4	36		T6	1		T10	3
valid_sources[0x47]	20304	1		T4	22		T7	1		T9	5
valid_sources[0x48]	18738	1		T4	17		T6	1		T7	7
valid_sources[0x49]	20272	1		T4	50		T6	1		T8	20
valid_sources[0x4a]	19156	1		T4	20		T6	2		T7	8
valid_sources[0x4b]	19629	1		T4	23		T6	3		T7	5
valid_sources[0x4c]	18365	1		T4	27		T7	2		T9	3
valid_sources[0x4d]	20833	1		T4	35		T6	2		T40	4
valid_sources[0x4e]	19503	1		T4	33		T7	1		T8	14
valid_sources[0x4f]	19500	1		T4	19		T9	6		T15	394
valid_sources[0x50]	19418	1		T4	24		T6	1		T7	3
valid_sources[0x51]	19850	1		T4	23		T6	2		T9	1
valid_sources[0x52]	18742	1		T4	16		T9	1		T23	2
valid_sources[0x53]	18346	1		T4	30		T6	4		T7	3
valid_sources[0x54]	17543	1		T4	21		T9	4		T40	2
valid_sources[0x55]	18356	1		T4	24		T6	1		T9	4
valid_sources[0x56]	18500	1		T4	27		T6	1		T8	24
valid_sources[0x57]	18973	1		T4	24		T6	2		T194	1
valid_sources[0x58]	19202	1		T4	30		T6	1		T7	1
valid_sources[0x59]	20563	1		T3	1		T4	21		T6	1
valid_sources[0x5a]	17952	1		T4	24		T6	1		T7	2
valid_sources[0x5b]	19631	1		T4	44		T9	1		T40	2
valid_sources[0x5c]	19326	1		T4	24		T6	1		T7	5
valid_sources[0x5d]	18529	1		T4	23		T7	4		T9	5
valid_sources[0x5e]	19788	1		T4	42		T24	3		T40	1
valid_sources[0x5f]	18857	1		T4	25		T7	1		T24	2
valid_sources[0x60]	20214	1		T4	21		T6	1		T7	1
valid_sources[0x61]	19132	1		T4	38		T6	1		T24	3
valid_sources[0x62]	19065	1		T4	27		T6	5		T7	2
valid_sources[0x63]	19741	1		T3	2		T4	27		T7	4
valid_sources[0x64]	17979	1		T4	22		T6	1		T9	2
valid_sources[0x65]	19524	1		T4	23		T6	1		T9	3
valid_sources[0x66]	19186	1		T4	30		T6	2		T9	1
valid_sources[0x67]	19463	1		T4	32		T6	3		T9	5
valid_sources[0x68]	19254	1		T1	1		T4	25		T7	2
valid_sources[0x69]	20159	1		T4	21		T194	1		T40	1
valid_sources[0x6a]	19658	1		T4	27		T9	1		T40	3
valid_sources[0x6b]	19662	1		T4	27		T9	6		T24	2
valid_sources[0x6c]	20431	1		T2	1		T4	30		T24	2
valid_sources[0x6d]	18016	1		T4	17		T6	2		T9	1
valid_sources[0x6e]	18244	1		T1	4		T4	36		T24	1
valid_sources[0x6f]	19656	1		T4	20		T6	1		T9	2
valid_sources[0x70]	19681	1		T1	1		T4	26		T6	1
valid_sources[0x71]	20293	1		T4	26		T7	2		T12	2
valid_sources[0x72]	18891	1		T4	24		T5	48		T7	1
valid_sources[0x73]	19431	1		T4	26		T8	14		T9	4
valid_sources[0x74]	21067	1		T4	20		T6	2		T12	1
valid_sources[0x75]	20428	1		T4	24		T6	1		T23	1
valid_sources[0x76]	19871	1		T4	23		T6	1		T7	2
valid_sources[0x77]	19931	1		T4	36		T6	1		T7	2
valid_sources[0x78]	19743	1		T2	3		T4	21		T7	2
valid_sources[0x79]	20113	1		T1	3		T4	37		T6	2
valid_sources[0x7a]	19381	1		T4	23		T5	57		T9	3
valid_sources[0x7b]	19976	1		T2	1		T4	31		T7	2
valid_sources[0x7c]	18565	1		T4	11		T6	4		T24	3
valid_sources[0x7d]	19166	1		T4	25		T6	1		T7	2
valid_sources[0x7e]	18890	1		T2	2		T4	30		T9	3
valid_sources[0x7f]	19648	1		T4	26		T7	1		T9	1
valid_sources[0x80]	19986	1		T4	31		T6	1		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1135979

1

T1

1

T4

1647

T5

15

values[0x0]

all_enables

biggest_size

1711798

1

T1

6

T2

9

T3

6

values[0x1]

all_enables

biggest_size

1709887

1

T1

8

T2

5

T3

6