Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	720284649	5399475	0	0
wdog_bark_thold_rd_A	720284649	166338	0	0
wdog_bite_thold_rd_A	720284649	146849	0	0
wdog_ctrl_rd_A	720284649	145198	0	0
wdog_regwen_rd_A	720284649	166814	0	0
wkup_ctrl_rd_A	720284649	146927	0	0
wkup_thold_hi_rd_A	720284649	169151	0	0
wkup_thold_lo_rd_A	720284649	145669	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720284649	5399475	0	0
T4	482208	7521	0	0
T5	431253	0	0	0
T6	892759	0	0	0
T7	836052	0	0	0
T8	154064	0	0	0
T9	526112	0	0	0
T10	22516	0	0	0
T11	403525	0	0	0
T12	168046	0	0	0
T15	0	113723	0	0
T16	0	323961	0	0
T21	21834	0	0	0
T33	0	93992	0	0
T34	0	79457	0	0
T35	0	147821	0	0
T36	0	111381	0	0
T37	0	39390	0	0
T38	0	150366	0	0
T39	0	103170	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720284649	166338	0	0
T4	482208	311	0	0
T5	431253	0	0	0
T6	892759	0	0	0
T7	836052	0	0	0
T8	154064	0	0	0
T9	526112	0	0	0
T10	22516	0	0	0
T11	403525	0	0	0
T12	168046	0	0	0
T21	21834	0	0	0
T33	0	8846	0	0
T35	0	14925	0	0
T36	0	5673	0	0
T37	0	3787	0	0
T38	0	16039	0	0
T39	0	5290	0	0
T42	0	12607	0	0
T88	0	5424	0	0
T89	0	12326	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720284649	146849	0	0
T4	482208	330	0	0
T5	431253	0	0	0
T6	892759	0	0	0
T7	836052	0	0	0
T8	154064	0	0	0
T9	526112	0	0	0
T10	22516	0	0	0
T11	403525	0	0	0
T12	168046	0	0	0
T21	21834	0	0	0
T33	0	7298	0	0
T35	0	13444	0	0
T36	0	5179	0	0
T37	0	3086	0	0
T38	0	13612	0	0
T39	0	4625	0	0
T42	0	11572	0	0
T88	0	4426	0	0
T89	0	11374	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720284649	145198	0	0
T4	482208	369	0	0
T5	431253	0	0	0
T6	892759	0	0	0
T7	836052	0	0	0
T8	154064	0	0	0
T9	526112	0	0	0
T10	22516	0	0	0
T11	403525	0	0	0
T12	168046	0	0	0
T21	21834	0	0	0
T33	0	7174	0	0
T35	0	13157	0	0
T36	0	5004	0	0
T37	0	3221	0	0
T38	0	13698	0	0
T39	0	4704	0	0
T42	0	11151	0	0
T88	0	5068	0	0
T89	0	10874	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720284649	166814	0	0
T4	482208	271	0	0
T5	431253	0	0	0
T6	892759	0	0	0
T7	836052	0	0	0
T8	154064	0	0	0
T9	526112	0	0	0
T10	22516	0	0	0
T11	403525	0	0	0
T12	168046	0	0	0
T21	21834	0	0	0
T33	0	8905	0	0
T35	0	14638	0	0
T36	0	5642	0	0
T37	0	3684	0	0
T38	0	15533	0	0
T39	0	5213	0	0
T42	0	12914	0	0
T88	0	5743	0	0
T89	0	12854	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720284649	146927	0	0
T4	482208	315	0	0
T5	431253	0	0	0
T6	892759	0	0	0
T7	836052	0	0	0
T8	154064	0	0	0
T9	526112	0	0	0
T10	22516	0	0	0
T11	403525	0	0	0
T12	168046	0	0	0
T21	21834	0	0	0
T33	0	7879	0	0
T35	0	12702	0	0
T36	0	5074	0	0
T37	0	3584	0	0
T38	0	13673	0	0
T39	0	4616	0	0
T42	0	11010	0	0
T88	0	4637	0	0
T89	0	11036	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720284649	169151	0	0
T4	482208	386	0	0
T5	431253	0	0	0
T6	892759	0	0	0
T7	836052	0	0	0
T8	154064	0	0	0
T9	526112	0	0	0
T10	22516	0	0	0
T11	403525	0	0	0
T12	168046	0	0	0
T21	21834	0	0	0
T33	0	8973	0	0
T35	0	15368	0	0
T36	0	5913	0	0
T37	0	3845	0	0
T38	0	15124	0	0
T39	0	5526	0	0
T42	0	12832	0	0
T88	0	5511	0	0
T89	0	12738	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720284649	145669	0	0
T4	482208	254	0	0
T5	431253	0	0	0
T6	892759	0	0	0
T7	836052	0	0	0
T8	154064	0	0	0
T9	526112	0	0	0
T10	22516	0	0	0
T11	403525	0	0	0
T12	168046	0	0	0
T21	21834	0	0	0
T33	0	7700	0	0
T35	0	13436	0	0
T36	0	4792	0	0
T37	0	3508	0	0
T38	0	13194	0	0
T39	0	4506	0	0
T42	0	11309	0	0
T88	0	4591	0	0
T89	0	11138	0	0