Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 16 | 15 | 93.75 |
Logical | 16 | 15 | 93.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T28,T29,T30 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T25,T26,T27 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
40421456 |
0 |
0 |
T1 |
2650670 |
26849 |
0 |
0 |
T2 |
190060 |
14582 |
0 |
0 |
T3 |
500390 |
25125 |
0 |
0 |
T4 |
4822080 |
750234 |
0 |
0 |
T5 |
4312530 |
48185 |
0 |
0 |
T6 |
8927590 |
338691 |
0 |
0 |
T7 |
8360520 |
66356 |
0 |
0 |
T8 |
1540640 |
64622 |
0 |
0 |
T9 |
5261120 |
117013 |
0 |
0 |
T10 |
0 |
12017 |
0 |
0 |
T11 |
4035250 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32837050 |
31874660 |
0 |
0 |
T1 |
57000 |
56110 |
0 |
0 |
T2 |
760 |
170 |
0 |
0 |
T3 |
1010 |
220 |
0 |
0 |
T4 |
10030 |
8790 |
0 |
0 |
T5 |
718730 |
710920 |
0 |
0 |
T6 |
185980 |
178160 |
0 |
0 |
T7 |
79610 |
70740 |
0 |
0 |
T8 |
13380 |
7270 |
0 |
0 |
T9 |
438420 |
429260 |
0 |
0 |
T11 |
15510 |
30 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
46417 |
0 |
0 |
T1 |
2650670 |
16 |
0 |
0 |
T2 |
190060 |
18 |
0 |
0 |
T3 |
500390 |
15 |
0 |
0 |
T4 |
4822080 |
446 |
0 |
0 |
T5 |
4312530 |
246 |
0 |
0 |
T6 |
8927590 |
174 |
0 |
0 |
T7 |
8360520 |
181 |
0 |
0 |
T8 |
1540640 |
169 |
0 |
0 |
T9 |
5261120 |
282 |
0 |
0 |
T10 |
0 |
15 |
0 |
0 |
T11 |
4035250 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2650670 |
2650590 |
0 |
0 |
T2 |
190060 |
189130 |
0 |
0 |
T3 |
500390 |
499890 |
0 |
0 |
T4 |
4822080 |
4696730 |
0 |
0 |
T5 |
4312530 |
4311790 |
0 |
0 |
T6 |
8927590 |
8926800 |
0 |
0 |
T7 |
8360520 |
8351290 |
0 |
0 |
T8 |
1540640 |
1533100 |
0 |
0 |
T9 |
5261120 |
5260210 |
0 |
0 |
T11 |
4035250 |
4019160 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
5195409 |
0 |
0 |
T1 |
265067 |
3240 |
0 |
0 |
T2 |
19006 |
2430 |
0 |
0 |
T3 |
50039 |
3324 |
0 |
0 |
T4 |
482208 |
103873 |
0 |
0 |
T5 |
431253 |
6952 |
0 |
0 |
T6 |
892759 |
49740 |
0 |
0 |
T7 |
836052 |
9904 |
0 |
0 |
T8 |
154064 |
9639 |
0 |
0 |
T9 |
526112 |
17319 |
0 |
0 |
T10 |
0 |
1689 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
6088 |
0 |
0 |
T1 |
265067 |
2 |
0 |
0 |
T2 |
19006 |
3 |
0 |
0 |
T3 |
50039 |
2 |
0 |
0 |
T4 |
482208 |
62 |
0 |
0 |
T5 |
431253 |
36 |
0 |
0 |
T6 |
892759 |
27 |
0 |
0 |
T7 |
836052 |
27 |
0 |
0 |
T8 |
154064 |
26 |
0 |
0 |
T9 |
526112 |
41 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
5525986 |
0 |
0 |
T1 |
265067 |
4628 |
0 |
0 |
T2 |
19006 |
1466 |
0 |
0 |
T3 |
50039 |
3315 |
0 |
0 |
T4 |
482208 |
108508 |
0 |
0 |
T5 |
431253 |
6480 |
0 |
0 |
T6 |
892759 |
46246 |
0 |
0 |
T7 |
836052 |
7966 |
0 |
0 |
T8 |
154064 |
7891 |
0 |
0 |
T9 |
526112 |
16131 |
0 |
0 |
T10 |
0 |
1686 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
6440 |
0 |
0 |
T1 |
265067 |
3 |
0 |
0 |
T2 |
19006 |
2 |
0 |
0 |
T3 |
50039 |
2 |
0 |
0 |
T4 |
482208 |
65 |
0 |
0 |
T5 |
431253 |
33 |
0 |
0 |
T6 |
892759 |
27 |
0 |
0 |
T7 |
836052 |
23 |
0 |
0 |
T8 |
154064 |
21 |
0 |
0 |
T9 |
526112 |
40 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
2849698 |
0 |
0 |
T1 |
265067 |
1851 |
0 |
0 |
T2 |
19006 |
725 |
0 |
0 |
T3 |
50039 |
1415 |
0 |
0 |
T4 |
482208 |
46024 |
0 |
0 |
T5 |
431253 |
2544 |
0 |
0 |
T6 |
892759 |
18320 |
0 |
0 |
T7 |
836052 |
3579 |
0 |
0 |
T8 |
154064 |
3384 |
0 |
0 |
T9 |
526112 |
6274 |
0 |
0 |
T10 |
0 |
720 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
3369 |
0 |
0 |
T1 |
265067 |
1 |
0 |
0 |
T2 |
19006 |
1 |
0 |
0 |
T3 |
50039 |
1 |
0 |
0 |
T4 |
482208 |
29 |
0 |
0 |
T5 |
431253 |
15 |
0 |
0 |
T6 |
892759 |
11 |
0 |
0 |
T7 |
836052 |
11 |
0 |
0 |
T8 |
154064 |
10 |
0 |
0 |
T9 |
526112 |
17 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
2838816 |
0 |
0 |
T1 |
265067 |
1853 |
0 |
0 |
T2 |
19006 |
727 |
0 |
0 |
T3 |
50039 |
1425 |
0 |
0 |
T4 |
482208 |
45114 |
0 |
0 |
T5 |
431253 |
2455 |
0 |
0 |
T6 |
892759 |
18418 |
0 |
0 |
T7 |
836052 |
3601 |
0 |
0 |
T8 |
154064 |
3382 |
0 |
0 |
T9 |
526112 |
6308 |
0 |
0 |
T10 |
0 |
722 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
3349 |
0 |
0 |
T1 |
265067 |
1 |
0 |
0 |
T2 |
19006 |
1 |
0 |
0 |
T3 |
50039 |
1 |
0 |
0 |
T4 |
482208 |
29 |
0 |
0 |
T5 |
431253 |
15 |
0 |
0 |
T6 |
892759 |
11 |
0 |
0 |
T7 |
836052 |
11 |
0 |
0 |
T8 |
154064 |
10 |
0 |
0 |
T9 |
526112 |
17 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
4827324 |
0 |
0 |
T1 |
265067 |
3247 |
0 |
0 |
T2 |
19006 |
1466 |
0 |
0 |
T3 |
50039 |
3296 |
0 |
0 |
T4 |
482208 |
90915 |
0 |
0 |
T5 |
431253 |
5728 |
0 |
0 |
T6 |
892759 |
37576 |
0 |
0 |
T7 |
836052 |
7645 |
0 |
0 |
T8 |
154064 |
7622 |
0 |
0 |
T9 |
526112 |
13789 |
0 |
0 |
T10 |
0 |
1676 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
5577 |
0 |
0 |
T1 |
265067 |
2 |
0 |
0 |
T2 |
19006 |
2 |
0 |
0 |
T3 |
50039 |
2 |
0 |
0 |
T4 |
482208 |
54 |
0 |
0 |
T5 |
431253 |
30 |
0 |
0 |
T6 |
892759 |
22 |
0 |
0 |
T7 |
836052 |
22 |
0 |
0 |
T8 |
154064 |
20 |
0 |
0 |
T9 |
526112 |
34 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
2863010 |
0 |
0 |
T1 |
265067 |
1849 |
0 |
0 |
T2 |
19006 |
723 |
0 |
0 |
T3 |
50039 |
1401 |
0 |
0 |
T4 |
482208 |
46304 |
0 |
0 |
T5 |
431253 |
2681 |
0 |
0 |
T6 |
892759 |
18260 |
0 |
0 |
T7 |
836052 |
3557 |
0 |
0 |
T8 |
154064 |
3288 |
0 |
0 |
T9 |
526112 |
6240 |
0 |
0 |
T10 |
0 |
718 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
3366 |
0 |
0 |
T1 |
265067 |
1 |
0 |
0 |
T2 |
19006 |
1 |
0 |
0 |
T3 |
50039 |
1 |
0 |
0 |
T4 |
482208 |
29 |
0 |
0 |
T5 |
431253 |
15 |
0 |
0 |
T6 |
892759 |
11 |
0 |
0 |
T7 |
836052 |
11 |
0 |
0 |
T8 |
154064 |
10 |
0 |
0 |
T9 |
526112 |
17 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
2832718 |
0 |
0 |
T1 |
265067 |
1847 |
0 |
0 |
T2 |
19006 |
721 |
0 |
0 |
T3 |
50039 |
1394 |
0 |
0 |
T4 |
482208 |
46062 |
0 |
0 |
T5 |
431253 |
2647 |
0 |
0 |
T6 |
892759 |
18182 |
0 |
0 |
T7 |
836052 |
3535 |
0 |
0 |
T8 |
154064 |
3314 |
0 |
0 |
T9 |
526112 |
6206 |
0 |
0 |
T10 |
0 |
712 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
3330 |
0 |
0 |
T1 |
265067 |
1 |
0 |
0 |
T2 |
19006 |
1 |
0 |
0 |
T3 |
50039 |
1 |
0 |
0 |
T4 |
482208 |
29 |
0 |
0 |
T5 |
431253 |
15 |
0 |
0 |
T6 |
892759 |
11 |
0 |
0 |
T7 |
836052 |
11 |
0 |
0 |
T8 |
154064 |
10 |
0 |
0 |
T9 |
526112 |
17 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
5681705 |
0 |
0 |
T1 |
265067 |
3245 |
0 |
0 |
T2 |
19006 |
3171 |
0 |
0 |
T3 |
50039 |
4820 |
0 |
0 |
T4 |
482208 |
114303 |
0 |
0 |
T5 |
431253 |
7954 |
0 |
0 |
T6 |
892759 |
57645 |
0 |
0 |
T7 |
836052 |
12055 |
0 |
0 |
T8 |
154064 |
12296 |
0 |
0 |
T9 |
526112 |
19566 |
0 |
0 |
T10 |
0 |
1701 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
6047 |
0 |
0 |
T1 |
265067 |
2 |
0 |
0 |
T2 |
19006 |
3 |
0 |
0 |
T3 |
50039 |
2 |
0 |
0 |
T4 |
482208 |
62 |
0 |
0 |
T5 |
431253 |
36 |
0 |
0 |
T6 |
892759 |
21 |
0 |
0 |
T7 |
836052 |
27 |
0 |
0 |
T8 |
154064 |
26 |
0 |
0 |
T9 |
526112 |
41 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
5350211 |
0 |
0 |
T1 |
265067 |
3236 |
0 |
0 |
T2 |
19006 |
2424 |
0 |
0 |
T3 |
50039 |
3305 |
0 |
0 |
T4 |
482208 |
104017 |
0 |
0 |
T5 |
431253 |
7924 |
0 |
0 |
T6 |
892759 |
54430 |
0 |
0 |
T7 |
836052 |
10690 |
0 |
0 |
T8 |
154064 |
10051 |
0 |
0 |
T9 |
526112 |
18196 |
0 |
0 |
T10 |
0 |
1669 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
6094 |
0 |
0 |
T1 |
265067 |
2 |
0 |
0 |
T2 |
19006 |
3 |
0 |
0 |
T3 |
50039 |
2 |
0 |
0 |
T4 |
482208 |
62 |
0 |
0 |
T5 |
431253 |
36 |
0 |
0 |
T6 |
892759 |
22 |
0 |
0 |
T7 |
836052 |
27 |
0 |
0 |
T8 |
154064 |
26 |
0 |
0 |
T9 |
526112 |
41 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
| Total | Covered | Percent |
Conditions | 16 | 15 | 93.75 |
Logical | 16 | 15 | 93.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T28,T29,T30 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T25,T26,T27 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
2456579 |
0 |
0 |
T1 |
265067 |
1853 |
0 |
0 |
T2 |
19006 |
729 |
0 |
0 |
T3 |
50039 |
1430 |
0 |
0 |
T4 |
482208 |
45114 |
0 |
0 |
T5 |
431253 |
2820 |
0 |
0 |
T6 |
892759 |
19874 |
0 |
0 |
T7 |
836052 |
3824 |
0 |
0 |
T8 |
154064 |
3755 |
0 |
0 |
T9 |
526112 |
6984 |
0 |
0 |
T10 |
0 |
724 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3283705 |
3187466 |
0 |
0 |
T1 |
5700 |
5611 |
0 |
0 |
T2 |
76 |
17 |
0 |
0 |
T3 |
101 |
22 |
0 |
0 |
T4 |
1003 |
879 |
0 |
0 |
T5 |
71873 |
71092 |
0 |
0 |
T6 |
18598 |
17816 |
0 |
0 |
T7 |
7961 |
7074 |
0 |
0 |
T8 |
1338 |
727 |
0 |
0 |
T9 |
43842 |
42926 |
0 |
0 |
T11 |
1551 |
3 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
2757 |
0 |
0 |
T1 |
265067 |
1 |
0 |
0 |
T2 |
19006 |
1 |
0 |
0 |
T3 |
50039 |
1 |
0 |
0 |
T4 |
482208 |
25 |
0 |
0 |
T5 |
431253 |
15 |
0 |
0 |
T6 |
892759 |
11 |
0 |
0 |
T7 |
836052 |
11 |
0 |
0 |
T8 |
154064 |
10 |
0 |
0 |
T9 |
526112 |
17 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
403525 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
720284649 |
719634731 |
0 |
0 |
T1 |
265067 |
265059 |
0 |
0 |
T2 |
19006 |
18913 |
0 |
0 |
T3 |
50039 |
49989 |
0 |
0 |
T4 |
482208 |
469673 |
0 |
0 |
T5 |
431253 |
431179 |
0 |
0 |
T6 |
892759 |
892680 |
0 |
0 |
T7 |
836052 |
835129 |
0 |
0 |
T8 |
154064 |
153310 |
0 |
0 |
T9 |
526112 |
526021 |
0 |
0 |
T11 |
403525 |
401916 |
0 |
0 |