Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	388018	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4759761	1		T1	13		T2	217		T3	150080

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1266032	1		T1	1		T2	22		T3	40004
values[0x0]	1819157	1		T1	9		T2	119		T3	57255
values[0x1]	2062590	1		T1	9		T2	150		T3	65185

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	172889	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4974890	1		T1	14		T2	236		T3	157001

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18561	1		T3	658		T4	324		T10	579
valid_sources[0x01]	19359	1		T2	1		T3	596		T4	327
valid_sources[0x02]	20750	1		T2	3		T3	594		T4	327
valid_sources[0x03]	19736	1		T3	720		T4	546		T10	599
valid_sources[0x04]	19794	1		T2	2		T3	677		T4	365
valid_sources[0x05]	20869	1		T3	562		T4	226		T10	534
valid_sources[0x06]	19077	1		T3	594		T4	317		T10	502
valid_sources[0x07]	22171	1		T1	1		T3	672		T4	331
valid_sources[0x08]	20693	1		T3	619		T4	182		T10	425
valid_sources[0x09]	20064	1		T1	1		T3	660		T4	381
valid_sources[0x0a]	21472	1		T3	643		T4	362		T10	488
valid_sources[0x0b]	19710	1		T2	1		T3	587		T4	431
valid_sources[0x0c]	22105	1		T2	1		T3	720		T4	347
valid_sources[0x0d]	18154	1		T2	1		T3	649		T4	321
valid_sources[0x0e]	20115	1		T2	5		T3	643		T4	252
valid_sources[0x0f]	19561	1		T1	1		T2	1		T3	658
valid_sources[0x10]	19908	1		T2	3		T3	642		T4	195
valid_sources[0x11]	20587	1		T2	3		T3	673		T4	248
valid_sources[0x12]	19851	1		T2	5		T3	643		T4	176
valid_sources[0x13]	19956	1		T2	2		T3	614		T4	314
valid_sources[0x14]	21183	1		T3	596		T4	576		T10	524
valid_sources[0x15]	20921	1		T3	584		T4	367		T10	488
valid_sources[0x16]	19476	1		T2	3		T3	599		T4	408
valid_sources[0x17]	19974	1		T3	665		T4	517		T10	479
valid_sources[0x18]	22341	1		T2	2		T3	645		T4	494
valid_sources[0x19]	20129	1		T2	2		T3	603		T4	408
valid_sources[0x1a]	19530	1		T3	686		T4	476		T10	596
valid_sources[0x1b]	19258	1		T2	1		T3	606		T4	338
valid_sources[0x1c]	19133	1		T2	1		T3	674		T4	314
valid_sources[0x1d]	20283	1		T3	597		T4	411		T6	272
valid_sources[0x1e]	19711	1		T2	2		T3	636		T4	370
valid_sources[0x1f]	20845	1		T3	627		T4	234		T10	470
valid_sources[0x20]	20915	1		T2	2		T3	661		T4	502
valid_sources[0x21]	20033	1		T3	594		T4	351		T10	537
valid_sources[0x22]	20991	1		T3	659		T4	227		T10	640
valid_sources[0x23]	22138	1		T3	587		T4	383		T10	570
valid_sources[0x24]	18846	1		T3	636		T4	458		T10	531
valid_sources[0x25]	19531	1		T2	1		T3	748		T4	316
valid_sources[0x26]	19415	1		T2	2		T3	645		T4	258
valid_sources[0x27]	19427	1		T2	4		T3	625		T4	443
valid_sources[0x28]	18194	1		T3	585		T4	486		T10	544
valid_sources[0x29]	22270	1		T3	647		T4	452		T5	22
valid_sources[0x2a]	19907	1		T2	2		T3	684		T4	316
valid_sources[0x2b]	19358	1		T3	657		T4	466		T10	546
valid_sources[0x2c]	19810	1		T3	683		T4	423		T10	526
valid_sources[0x2d]	21465	1		T3	638		T4	596		T10	547
valid_sources[0x2e]	18716	1		T2	2		T3	667		T4	441
valid_sources[0x2f]	20369	1		T3	630		T4	292		T10	471
valid_sources[0x30]	21581	1		T3	581		T4	576		T10	529
valid_sources[0x31]	18817	1		T2	2		T3	635		T4	384
valid_sources[0x32]	19651	1		T3	555		T4	416		T10	531
valid_sources[0x33]	20026	1		T3	549		T4	591		T10	508
valid_sources[0x34]	20255	1		T2	1		T3	603		T4	380
valid_sources[0x35]	20048	1		T3	655		T4	347		T10	439
valid_sources[0x36]	19261	1		T2	2		T3	660		T4	386
valid_sources[0x37]	21585	1		T3	629		T4	511		T10	542
valid_sources[0x38]	20612	1		T3	666		T4	482		T10	530
valid_sources[0x39]	19157	1		T3	629		T4	202		T10	569
valid_sources[0x3a]	19814	1		T3	621		T4	412		T10	509
valid_sources[0x3b]	19749	1		T2	2		T3	607		T4	283
valid_sources[0x3c]	21312	1		T2	4		T3	635		T4	269
valid_sources[0x3d]	21408	1		T2	4		T3	625		T4	437
valid_sources[0x3e]	19133	1		T1	1		T3	661		T4	549
valid_sources[0x3f]	20845	1		T3	665		T4	276		T10	522
valid_sources[0x40]	19000	1		T3	625		T4	203		T10	447
valid_sources[0x41]	20741	1		T2	1		T3	615		T4	315
valid_sources[0x42]	19491	1		T2	1		T3	598		T4	197
valid_sources[0x43]	19265	1		T3	649		T4	310		T10	548
valid_sources[0x44]	19818	1		T2	1		T3	576		T4	214
valid_sources[0x45]	18671	1		T2	2		T3	604		T4	453
valid_sources[0x46]	20141	1		T3	559		T4	613		T8	1
valid_sources[0x47]	19506	1		T3	677		T4	268		T10	503
valid_sources[0x48]	19886	1		T3	632		T4	326		T8	1
valid_sources[0x49]	19129	1		T3	677		T4	388		T10	490
valid_sources[0x4a]	20677	1		T2	5		T3	706		T4	328
valid_sources[0x4b]	20655	1		T2	3		T3	691		T4	362
valid_sources[0x4c]	19283	1		T3	663		T4	514		T10	472
valid_sources[0x4d]	21472	1		T3	574		T4	483		T10	487
valid_sources[0x4e]	22409	1		T3	574		T4	440		T10	591
valid_sources[0x4f]	20829	1		T3	597		T4	463		T10	508
valid_sources[0x50]	18345	1		T2	2		T3	601		T4	297
valid_sources[0x51]	19177	1		T3	590		T4	449		T10	622
valid_sources[0x52]	20812	1		T2	2		T3	610		T4	324
valid_sources[0x53]	20236	1		T3	650		T4	404		T10	468
valid_sources[0x54]	18791	1		T3	599		T4	460		T8	1
valid_sources[0x55]	19584	1		T3	654		T4	292		T10	544
valid_sources[0x56]	20288	1		T1	1		T2	2		T3	689
valid_sources[0x57]	19502	1		T2	10		T3	646		T4	343
valid_sources[0x58]	20628	1		T3	604		T4	449		T10	550
valid_sources[0x59]	20087	1		T2	1		T3	677		T4	325
valid_sources[0x5a]	19134	1		T2	1		T3	692		T4	427
valid_sources[0x5b]	18836	1		T3	681		T4	411		T10	484
valid_sources[0x5c]	19734	1		T2	5		T3	631		T4	405
valid_sources[0x5d]	19271	1		T2	2		T3	659		T4	517
valid_sources[0x5e]	21279	1		T3	595		T4	517		T10	496
valid_sources[0x5f]	20123	1		T2	1		T3	645		T4	291
valid_sources[0x60]	17271	1		T3	578		T4	281		T10	513
valid_sources[0x61]	19690	1		T2	1		T3	633		T4	404
valid_sources[0x62]	21039	1		T2	5		T3	664		T4	558
valid_sources[0x63]	20528	1		T2	1		T3	639		T4	298
valid_sources[0x64]	18361	1		T3	598		T4	535		T10	555
valid_sources[0x65]	20540	1		T2	2		T3	706		T4	516
valid_sources[0x66]	20177	1		T3	700		T4	375		T10	581
valid_sources[0x67]	19150	1		T3	630		T4	349		T10	513
valid_sources[0x68]	20821	1		T3	591		T4	341		T10	513
valid_sources[0x69]	20565	1		T2	1		T3	572		T4	406
valid_sources[0x6a]	20502	1		T3	652		T4	283		T10	470
valid_sources[0x6b]	20359	1		T2	1		T3	648		T4	332
valid_sources[0x6c]	19060	1		T2	1		T3	678		T4	271
valid_sources[0x6d]	19230	1		T3	628		T4	437		T10	489
valid_sources[0x6e]	20606	1		T3	634		T4	298		T10	588
valid_sources[0x6f]	18979	1		T2	1		T3	651		T4	290
valid_sources[0x70]	19823	1		T2	1		T3	608		T4	325
valid_sources[0x71]	19706	1		T3	528		T4	240		T10	526
valid_sources[0x72]	20722	1		T3	683		T4	326		T10	412
valid_sources[0x73]	19462	1		T2	2		T3	627		T4	343
valid_sources[0x74]	18401	1		T3	659		T4	512		T10	558
valid_sources[0x75]	20549	1		T3	636		T4	345		T10	460
valid_sources[0x76]	18212	1		T2	1		T3	605		T4	441
valid_sources[0x77]	18914	1		T1	1		T3	597		T4	447
valid_sources[0x78]	19823	1		T2	2		T3	663		T4	231
valid_sources[0x79]	19706	1		T2	3		T3	671		T4	365
valid_sources[0x7a]	19865	1		T3	653		T4	405		T10	449
valid_sources[0x7b]	19425	1		T3	596		T4	350		T10	468
valid_sources[0x7c]	20883	1		T3	627		T4	394		T10	537
valid_sources[0x7d]	19445	1		T2	1		T3	631		T4	303
valid_sources[0x7e]	23140	1		T3	680		T4	391		T10	499
valid_sources[0x7f]	18029	1		T2	4		T3	667		T4	222
valid_sources[0x80]	19660	1		T3	691		T4	423		T10	497

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1187241

1

T2

16

T3

37586

T4

22843

values[0x0]

all_enables

biggest_size

1786673

1

T1

7

T2

91

T3

56314

values[0x1]

all_enables

biggest_size

1785847

1

T1

6

T2

110

T3

56180