Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	863970534	5658029	0	0
wdog_bark_thold_rd_A	863970534	137218	0	0
wdog_bite_thold_rd_A	863970534	121818	0	0
wdog_ctrl_rd_A	863970534	120951	0	0
wdog_regwen_rd_A	863970534	137063	0	0
wkup_ctrl_rd_A	863970534	121673	0	0
wkup_thold_hi_rd_A	863970534	138499	0	0
wkup_thold_lo_rd_A	863970534	122120	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	863970534	5658029	0	0
T3	743823	190736	0	0
T4	469641	108919	0	0
T5	2690	0	0	0
T6	387390	0	0	0
T7	230568	0	0	0
T8	39897	0	0	0
T9	435337	0	0	0
T10	603524	144101	0	0
T11	102370	0	0	0
T12	13845	0	0	0
T30	0	302664	0	0
T36	0	51818	0	0
T37	0	144766	0	0
T38	0	180321	0	0
T39	0	41427	0	0
T40	0	65487	0	0
T41	0	63397	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	863970534	137218	0	0
T4	469641	10754	0	0
T5	2690	0	0	0
T6	387390	0	0	0
T7	230568	0	0	0
T8	39897	0	0	0
T9	435337	0	0	0
T10	603524	7999	0	0
T11	102370	0	0	0
T12	13845	0	0	0
T28	18092	0	0	0
T39	0	4235	0	0
T40	0	6789	0	0
T56	0	17465	0	0
T86	0	13601	0	0
T87	0	21426	0	0
T88	0	9930	0	0
T89	0	12703	0	0
T90	0	11252	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	863970534	121818	0	0
T4	469641	9551	0	0
T5	2690	0	0	0
T6	387390	0	0	0
T7	230568	0	0	0
T8	39897	0	0	0
T9	435337	0	0	0
T10	603524	6651	0	0
T11	102370	0	0	0
T12	13845	0	0	0
T28	18092	0	0	0
T39	0	3949	0	0
T40	0	5826	0	0
T56	0	15809	0	0
T86	0	12144	0	0
T87	0	19262	0	0
T88	0	8542	0	0
T89	0	11442	0	0
T90	0	9955	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	863970534	120951	0	0
T4	469641	9645	0	0
T5	2690	0	0	0
T6	387390	0	0	0
T7	230568	0	0	0
T8	39897	0	0	0
T9	435337	0	0	0
T10	603524	6759	0	0
T11	102370	0	0	0
T12	13845	0	0	0
T28	18092	0	0	0
T39	0	3313	0	0
T40	0	5902	0	0
T56	0	15583	0	0
T86	0	12185	0	0
T87	0	18861	0	0
T88	0	8550	0	0
T89	0	11358	0	0
T90	0	9646	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	863970534	137063	0	0
T4	469641	10787	0	0
T5	2690	0	0	0
T6	387390	0	0	0
T7	230568	0	0	0
T8	39897	0	0	0
T9	435337	0	0	0
T10	603524	7412	0	0
T11	102370	0	0	0
T12	13845	0	0	0
T28	18092	0	0	0
T39	0	4114	0	0
T40	0	6671	0	0
T56	0	17404	0	0
T86	0	13667	0	0
T87	0	21926	0	0
T88	0	9394	0	0
T89	0	13192	0	0
T90	0	11139	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	863970534	121673	0	0
T4	469641	9074	0	0
T5	2690	0	0	0
T6	387390	0	0	0
T7	230568	0	0	0
T8	39897	0	0	0
T9	435337	0	0	0
T10	603524	6855	0	0
T11	102370	0	0	0
T12	13845	0	0	0
T28	18092	0	0	0
T39	0	3770	0	0
T40	0	5908	0	0
T56	0	15599	0	0
T86	0	12087	0	0
T87	0	18789	0	0
T88	0	8681	0	0
T89	0	11776	0	0
T90	0	9728	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	863970534	138499	0	0
T4	469641	11120	0	0
T5	2690	0	0	0
T6	387390	0	0	0
T7	230568	0	0	0
T8	39897	0	0	0
T9	435337	0	0	0
T10	603524	7912	0	0
T11	102370	0	0	0
T12	13845	0	0	0
T28	18092	0	0	0
T39	0	4236	0	0
T40	0	6592	0	0
T56	0	17954	0	0
T86	0	14015	0	0
T87	0	21463	0	0
T88	0	9588	0	0
T89	0	13080	0	0
T90	0	10787	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	863970534	122120	0	0
T4	469641	9395	0	0
T5	2690	0	0	0
T6	387390	0	0	0
T7	230568	0	0	0
T8	39897	0	0	0
T9	435337	0	0	0
T10	603524	6943	0	0
T11	102370	0	0	0
T12	13845	0	0	0
T28	18092	0	0	0
T39	0	3707	0	0
T40	0	5785	0	0
T56	0	15830	0	0
T86	0	12347	0	0
T87	0	19525	0	0
T88	0	8493	0	0
T89	0	11705	0	0
T90	0	9652	0	0