Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	355418	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4323487	1		T1	50232		T2	14		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1151778	1		T1	13273		T2	1		T3	1
values[0x0]	1651641	1		T1	19039		T2	11		T3	7
values[0x1]	1875486	1		T1	21692		T2	10		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158537	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4520368	1		T1	52314		T2	15		T3	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19080	1		T1	113		T10	1		T11	286
valid_sources[0x01]	17119	1		T1	190		T11	313		T16	205
valid_sources[0x02]	17564	1		T1	355		T5	2		T10	2
valid_sources[0x03]	17379	1		T1	224		T4	1		T5	2
valid_sources[0x04]	18146	1		T1	127		T10	3		T11	268
valid_sources[0x05]	18111	1		T1	288		T7	1		T11	379
valid_sources[0x06]	18577	1		T1	85		T5	1		T7	1
valid_sources[0x07]	17371	1		T1	29		T11	314		T16	195
valid_sources[0x08]	18171	1		T1	149		T5	4		T11	261
valid_sources[0x09]	16187	1		T1	67		T5	2		T8	2
valid_sources[0x0a]	17719	1		T1	375		T10	1		T11	371
valid_sources[0x0b]	17649	1		T1	753		T5	2		T11	309
valid_sources[0x0c]	17884	1		T1	84		T10	3		T11	325
valid_sources[0x0d]	20195	1		T1	143		T5	1		T7	1
valid_sources[0x0e]	18524	1		T1	211		T5	1		T10	2
valid_sources[0x0f]	17430	1		T1	183		T11	298		T16	213
valid_sources[0x10]	18091	1		T1	167		T5	2		T8	1
valid_sources[0x11]	18678	1		T1	67		T11	383		T16	206
valid_sources[0x12]	16627	1		T1	107		T5	2		T6	1
valid_sources[0x13]	17585	1		T1	96		T5	2		T11	282
valid_sources[0x14]	16952	1		T1	594		T5	2		T9	3
valid_sources[0x15]	19260	1		T1	133		T10	3		T11	289
valid_sources[0x16]	17760	1		T1	190		T5	1		T11	363
valid_sources[0x17]	16296	1		T1	263		T11	307		T16	193
valid_sources[0x18]	17712	1		T1	317		T5	1		T10	1
valid_sources[0x19]	17347	1		T1	176		T11	313		T23	4
valid_sources[0x1a]	17367	1		T1	84		T11	280		T16	209
valid_sources[0x1b]	16836	1		T1	190		T4	1		T10	3
valid_sources[0x1c]	17264	1		T1	235		T5	4		T10	11
valid_sources[0x1d]	17990	1		T1	144		T5	1		T11	315
valid_sources[0x1e]	20704	1		T1	109		T5	1		T11	291
valid_sources[0x1f]	19141	1		T1	592		T10	3		T11	241
valid_sources[0x20]	20070	1		T1	422		T10	1		T11	315
valid_sources[0x21]	20016	1		T1	27		T8	1		T10	3
valid_sources[0x22]	18435	1		T1	149		T11	269		T23	6
valid_sources[0x23]	19485	1		T1	22		T5	1		T10	5
valid_sources[0x24]	17682	1		T1	101		T8	3		T10	1
valid_sources[0x25]	18270	1		T1	84		T5	5		T10	3
valid_sources[0x26]	20154	1		T1	68		T5	2		T7	1
valid_sources[0x27]	17712	1		T1	60		T5	2		T9	1
valid_sources[0x28]	20337	1		T1	10		T5	1		T11	326
valid_sources[0x29]	19687	1		T1	269		T3	1		T11	293
valid_sources[0x2a]	18598	1		T1	303		T5	2		T11	326
valid_sources[0x2b]	17715	1		T1	291		T10	8		T11	280
valid_sources[0x2c]	17252	1		T1	223		T4	1		T11	283
valid_sources[0x2d]	18183	1		T1	16		T10	4		T11	239
valid_sources[0x2e]	16943	1		T1	117		T4	1		T5	4
valid_sources[0x2f]	17774	1		T1	119		T5	2		T11	271
valid_sources[0x30]	18036	1		T1	22		T5	1		T10	3
valid_sources[0x31]	19904	1		T1	29		T5	1		T10	4
valid_sources[0x32]	19516	1		T1	535		T11	279		T16	201
valid_sources[0x33]	18328	1		T1	122		T5	1		T10	1
valid_sources[0x34]	17906	1		T1	141		T5	1		T11	332
valid_sources[0x35]	18446	1		T1	122		T5	1		T10	2
valid_sources[0x36]	18374	1		T1	165		T5	4		T6	2
valid_sources[0x37]	19675	1		T1	451		T5	1		T11	298
valid_sources[0x38]	17862	1		T1	266		T9	4		T11	239
valid_sources[0x39]	19563	1		T1	226		T9	1		T10	3
valid_sources[0x3a]	19928	1		T1	193		T3	5		T5	5
valid_sources[0x3b]	19071	1		T1	94		T10	3		T11	320
valid_sources[0x3c]	19081	1		T1	182		T5	2		T11	271
valid_sources[0x3d]	17985	1		T1	231		T5	1		T11	354
valid_sources[0x3e]	19029	1		T1	47		T11	252		T16	231
valid_sources[0x3f]	18829	1		T1	35		T5	1		T10	4
valid_sources[0x40]	20517	1		T1	338		T5	1		T6	2
valid_sources[0x41]	19605	1		T1	255		T5	4		T11	305
valid_sources[0x42]	19717	1		T1	507		T7	1		T11	324
valid_sources[0x43]	18423	1		T1	40		T10	1		T11	348
valid_sources[0x44]	18423	1		T1	162		T5	1		T11	274
valid_sources[0x45]	21030	1		T1	24		T5	3		T10	4
valid_sources[0x46]	19314	1		T1	347		T5	2		T10	1
valid_sources[0x47]	20193	1		T1	340		T10	6		T11	292
valid_sources[0x48]	16646	1		T1	124		T11	304		T23	8
valid_sources[0x49]	19175	1		T1	364		T5	2		T11	281
valid_sources[0x4a]	18239	1		T1	341		T5	2		T11	308
valid_sources[0x4b]	18853	1		T1	126		T11	224		T16	224
valid_sources[0x4c]	16344	1		T1	240		T11	357		T13	1
valid_sources[0x4d]	16717	1		T1	178		T5	1		T10	1
valid_sources[0x4e]	18468	1		T1	428		T8	1		T10	1
valid_sources[0x4f]	19006	1		T1	33		T5	3		T10	3
valid_sources[0x50]	18103	1		T1	72		T5	2		T11	268
valid_sources[0x51]	16231	1		T1	176		T3	1		T5	1
valid_sources[0x52]	17745	1		T1	437		T5	1		T11	329
valid_sources[0x53]	18851	1		T1	428		T5	2		T10	1
valid_sources[0x54]	20471	1		T1	37		T11	288		T15	1
valid_sources[0x55]	19380	1		T1	254		T5	5		T10	5
valid_sources[0x56]	19853	1		T1	442		T5	2		T11	335
valid_sources[0x57]	19420	1		T1	382		T11	310		T15	1
valid_sources[0x58]	18386	1		T1	164		T5	3		T6	1
valid_sources[0x59]	17262	1		T1	333		T5	2		T11	280
valid_sources[0x5a]	18422	1		T1	11		T10	4		T11	236
valid_sources[0x5b]	18638	1		T1	322		T5	2		T11	259
valid_sources[0x5c]	17770	1		T1	302		T5	1		T7	1
valid_sources[0x5d]	17386	1		T1	14		T5	3		T11	210
valid_sources[0x5e]	18732	1		T1	153		T5	3		T7	1
valid_sources[0x5f]	20701	1		T1	320		T10	4		T11	279
valid_sources[0x60]	16749	1		T1	123		T5	1		T10	9
valid_sources[0x61]	18078	1		T1	323		T5	1		T8	2
valid_sources[0x62]	17249	1		T1	264		T5	3		T11	263
valid_sources[0x63]	19069	1		T1	139		T5	2		T10	6
valid_sources[0x64]	18650	1		T1	67		T5	4		T6	4
valid_sources[0x65]	19703	1		T1	331		T5	3		T10	9
valid_sources[0x66]	17883	1		T1	645		T10	5		T11	289
valid_sources[0x67]	17658	1		T1	329		T11	243		T16	201
valid_sources[0x68]	18980	1		T1	104		T11	252		T23	6
valid_sources[0x69]	17302	1		T1	163		T5	2		T11	310
valid_sources[0x6a]	17159	1		T1	289		T10	3		T11	379
valid_sources[0x6b]	16401	1		T1	41		T7	1		T11	336
valid_sources[0x6c]	19088	1		T1	197		T10	4		T11	333
valid_sources[0x6d]	19143	1		T1	341		T11	295		T16	241
valid_sources[0x6e]	18735	1		T1	316		T5	2		T11	348
valid_sources[0x6f]	18224	1		T1	220		T5	1		T11	275
valid_sources[0x70]	19186	1		T1	164		T5	3		T10	3
valid_sources[0x71]	16315	1		T1	17		T4	1		T7	1
valid_sources[0x72]	17013	1		T1	140		T5	3		T11	299
valid_sources[0x73]	18280	1		T1	345		T10	5		T11	296
valid_sources[0x74]	17293	1		T1	444		T5	4		T11	303
valid_sources[0x75]	19030	1		T1	362		T5	2		T11	263
valid_sources[0x76]	17226	1		T1	301		T4	2		T11	280
valid_sources[0x77]	18564	1		T1	101		T5	4		T10	5
valid_sources[0x78]	18668	1		T1	48		T5	2		T7	1
valid_sources[0x79]	19641	1		T1	214		T5	2		T10	1
valid_sources[0x7a]	18041	1		T1	133		T10	1		T11	323
valid_sources[0x7b]	18893	1		T1	95		T5	1		T10	3
valid_sources[0x7c]	16732	1		T1	251		T11	315		T16	208
valid_sources[0x7d]	19508	1		T1	13		T8	2		T10	4
valid_sources[0x7e]	17871	1		T1	236		T5	1		T10	1
valid_sources[0x7f]	18297	1		T1	266		T11	318		T16	231
valid_sources[0x80]	17881	1		T1	251		T5	1		T11	281

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1079926

1

T1

12551

T5

18

T7

1

values[0x0]

all_enables

biggest_size

1621460

1

T1

18724

T2

8

T3

6

values[0x1]

all_enables

biggest_size

1622101

1

T1

18957

T2

6

T3

6