Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	731653601	5114495	0	0
wdog_bark_thold_rd_A	731653601	138026	0	0
wdog_bite_thold_rd_A	731653601	123929	0	0
wdog_ctrl_rd_A	731653601	121628	0	0
wdog_regwen_rd_A	731653601	139829	0	0
wkup_ctrl_rd_A	731653601	122229	0	0
wkup_thold_hi_rd_A	731653601	139778	0	0
wkup_thold_lo_rd_A	731653601	121354	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731653601	5114495	0	0
T1	249963	54962	0	0
T2	11594	0	0	0
T3	325936	0	0	0
T4	226283	0	0	0
T5	277052	0	0	0
T6	139592	0	0	0
T7	162540	0	0	0
T8	355556	0	0	0
T9	26548	0	0	0
T10	279644	0	0	0
T11	0	83636	0	0
T16	0	59983	0	0
T25	0	46782	0	0
T27	0	63386	0	0
T29	0	79328	0	0
T30	0	123904	0	0
T40	0	75126	0	0
T41	0	91364	0	0
T42	0	240959	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731653601	138026	0	0
T1	249963	5599	0	0
T2	11594	0	0	0
T3	325936	0	0	0
T4	226283	0	0	0
T5	277052	0	0	0
T6	139592	0	0	0
T7	162540	0	0	0
T8	355556	0	0	0
T9	26548	0	0	0
T10	279644	0	0	0
T11	0	4442	0	0
T16	0	5906	0	0
T25	0	4804	0	0
T29	0	8081	0	0
T84	0	11074	0	0
T85	0	2705	0	0
T86	0	7132	0	0
T87	0	4302	0	0
T88	0	8518	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731653601	123929	0	0
T1	249963	4890	0	0
T2	11594	0	0	0
T3	325936	0	0	0
T4	226283	0	0	0
T5	277052	0	0	0
T6	139592	0	0	0
T7	162540	0	0	0
T8	355556	0	0	0
T9	26548	0	0	0
T10	279644	0	0	0
T11	0	4065	0	0
T16	0	5230	0	0
T25	0	4245	0	0
T29	0	7260	0	0
T84	0	10226	0	0
T85	0	2409	0	0
T86	0	6557	0	0
T87	0	3663	0	0
T88	0	7759	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731653601	121628	0	0
T1	249963	5142	0	0
T2	11594	0	0	0
T3	325936	0	0	0
T4	226283	0	0	0
T5	277052	0	0	0
T6	139592	0	0	0
T7	162540	0	0	0
T8	355556	0	0	0
T9	26548	0	0	0
T10	279644	0	0	0
T11	0	4038	0	0
T16	0	5068	0	0
T25	0	4422	0	0
T29	0	7261	0	0
T84	0	9951	0	0
T85	0	2327	0	0
T86	0	6368	0	0
T87	0	3717	0	0
T88	0	7565	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731653601	139829	0	0
T1	249963	6127	0	0
T2	11594	0	0	0
T3	325936	0	0	0
T4	226283	0	0	0
T5	277052	0	0	0
T6	139592	0	0	0
T7	162540	0	0	0
T8	355556	0	0	0
T9	26548	0	0	0
T10	279644	0	0	0
T11	0	4438	0	0
T16	0	6053	0	0
T25	0	4937	0	0
T29	0	7929	0	0
T84	0	11528	0	0
T85	0	2568	0	0
T86	0	7270	0	0
T87	0	4001	0	0
T88	0	8304	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731653601	122229	0	0
T1	249963	5022	0	0
T2	11594	0	0	0
T3	325936	0	0	0
T4	226283	0	0	0
T5	277052	0	0	0
T6	139592	0	0	0
T7	162540	0	0	0
T8	355556	0	0	0
T9	26548	0	0	0
T10	279644	0	0	0
T11	0	4014	0	0
T16	0	5093	0	0
T25	0	4458	0	0
T29	0	7083	0	0
T84	0	10276	0	0
T85	0	2239	0	0
T86	0	6330	0	0
T87	0	3657	0	0
T88	0	7824	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731653601	139778	0	0
T1	249963	5894	0	0
T2	11594	0	0	0
T3	325936	0	0	0
T4	226283	0	0	0
T5	277052	0	0	0
T6	139592	0	0	0
T7	162540	0	0	0
T8	355556	0	0	0
T9	26548	0	0	0
T10	279644	0	0	0
T11	0	4351	0	0
T16	0	5978	0	0
T25	0	5124	0	0
T29	0	7903	0	0
T84	0	11859	0	0
T85	0	2841	0	0
T86	0	7123	0	0
T87	0	4200	0	0
T88	0	8391	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731653601	121354	0	0
T1	249963	5327	0	0
T2	11594	0	0	0
T3	325936	0	0	0
T4	226283	0	0	0
T5	277052	0	0	0
T6	139592	0	0	0
T7	162540	0	0	0
T8	355556	0	0	0
T9	26548	0	0	0
T10	279644	0	0	0
T11	0	4032	0	0
T16	0	5047	0	0
T25	0	4265	0	0
T29	0	7000	0	0
T84	0	10241	0	0
T85	0	2108	0	0
T86	0	6138	0	0
T87	0	3724	0	0
T88	0	7511	0	0