Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	313777	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3782469	1		T1	16		T2	13		T3	235

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1007192	1		T1	1		T2	1		T3	27
values[0x0]	1446352	1		T1	12		T2	10		T3	145
values[0x1]	1642702	1		T1	9		T2	9		T3	170

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	139869	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3956377	1		T1	17		T2	16		T3	257

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16500	1		T33	3		T15	388		T18	162
valid_sources[0x01]	16358	1		T15	12		T18	157		T19	457
valid_sources[0x02]	16240	1		T15	132		T18	139		T19	497
valid_sources[0x03]	17013	1		T2	20		T15	25		T18	158
valid_sources[0x04]	15354	1		T1	1		T12	3		T15	149
valid_sources[0x05]	15795	1		T15	12		T18	142		T19	250
valid_sources[0x06]	16242	1		T13	1		T15	368		T18	153
valid_sources[0x07]	15780	1		T12	1		T15	160		T18	126
valid_sources[0x08]	15317	1		T7	1		T9	1		T15	153
valid_sources[0x09]	16292	1		T15	228		T18	146		T19	353
valid_sources[0x0a]	14826	1		T198	1		T15	19		T18	105
valid_sources[0x0b]	15345	1		T15	87		T18	145		T19	22
valid_sources[0x0c]	16600	1		T15	399		T18	151		T19	129
valid_sources[0x0d]	15257	1		T13	2		T15	110		T18	125
valid_sources[0x0e]	14877	1		T5	1		T15	96		T18	133
valid_sources[0x0f]	15397	1		T12	3		T35	1		T15	105
valid_sources[0x10]	15658	1		T15	14		T18	156		T19	305
valid_sources[0x11]	15457	1		T1	1		T15	9		T18	145
valid_sources[0x12]	17708	1		T12	2		T15	191		T18	129
valid_sources[0x13]	13949	1		T12	1		T15	24		T18	166
valid_sources[0x14]	15048	1		T15	212		T18	117		T19	163
valid_sources[0x15]	15921	1		T14	2		T15	14		T50	2
valid_sources[0x16]	15552	1		T6	1		T15	5		T18	133
valid_sources[0x17]	16596	1		T15	75		T18	172		T19	248
valid_sources[0x18]	16723	1		T15	217		T18	152		T51	1
valid_sources[0x19]	15574	1		T15	30		T18	136		T19	238
valid_sources[0x1a]	15250	1		T15	18		T18	140		T19	264
valid_sources[0x1b]	16845	1		T15	108		T18	131		T19	188
valid_sources[0x1c]	15000	1		T35	1		T15	53		T18	161
valid_sources[0x1d]	17202	1		T9	1		T13	1		T15	259
valid_sources[0x1e]	16672	1		T15	246		T18	170		T19	158
valid_sources[0x1f]	16491	1		T12	3		T15	166		T18	182
valid_sources[0x20]	16073	1		T7	2		T15	12		T18	121
valid_sources[0x21]	16350	1		T12	4		T15	13		T18	128
valid_sources[0x22]	16719	1		T15	24		T18	147		T19	85
valid_sources[0x23]	16440	1		T13	1		T15	202		T16	7
valid_sources[0x24]	15958	1		T15	412		T18	136		T19	613
valid_sources[0x25]	14685	1		T35	1		T15	328		T18	129
valid_sources[0x26]	15873	1		T12	3		T35	1		T15	7
valid_sources[0x27]	16926	1		T15	83		T17	1		T18	188
valid_sources[0x28]	15713	1		T198	1		T13	1		T15	379
valid_sources[0x29]	15861	1		T15	110		T18	132		T51	1
valid_sources[0x2a]	17666	1		T12	2		T15	27		T18	115
valid_sources[0x2b]	17406	1		T12	1		T15	77		T18	149
valid_sources[0x2c]	16032	1		T9	1		T12	23		T15	263
valid_sources[0x2d]	16239	1		T12	1		T18	150		T19	447
valid_sources[0x2e]	15980	1		T12	1		T15	42		T50	6
valid_sources[0x2f]	16148	1		T198	1		T15	294		T18	121
valid_sources[0x30]	16053	1		T12	1		T15	205		T18	127
valid_sources[0x31]	14569	1		T15	209		T18	156		T19	154
valid_sources[0x32]	15132	1		T199	2		T15	243		T18	158
valid_sources[0x33]	14530	1		T5	1		T12	2		T15	105
valid_sources[0x34]	16374	1		T7	1		T12	2		T15	17
valid_sources[0x35]	17395	1		T15	371		T18	138		T19	567
valid_sources[0x36]	15071	1		T15	41		T18	161		T19	701
valid_sources[0x37]	14600	1		T35	1		T15	10		T18	169
valid_sources[0x38]	15030	1		T12	1		T15	15		T18	146
valid_sources[0x39]	17462	1		T15	97		T18	133		T19	256
valid_sources[0x3a]	16439	1		T15	65		T18	159		T19	648
valid_sources[0x3b]	16144	1		T15	198		T17	1		T18	152
valid_sources[0x3c]	16204	1		T15	7		T18	151		T19	163
valid_sources[0x3d]	15483	1		T5	1		T7	1		T9	1
valid_sources[0x3e]	15772	1		T12	1		T199	1		T15	157
valid_sources[0x3f]	15682	1		T15	164		T18	158		T19	509
valid_sources[0x40]	16226	1		T1	1		T15	106		T17	1
valid_sources[0x41]	14681	1		T12	2		T15	27		T18	144
valid_sources[0x42]	17862	1		T199	1		T15	285		T18	136
valid_sources[0x43]	14705	1		T5	1		T12	1		T15	357
valid_sources[0x44]	18681	1		T15	22		T18	170		T19	326
valid_sources[0x45]	16894	1		T3	342		T9	1		T11	338
valid_sources[0x46]	16673	1		T15	108		T16	1		T18	154
valid_sources[0x47]	14663	1		T7	1		T14	1		T15	138
valid_sources[0x48]	15117	1		T12	6		T13	1		T15	9
valid_sources[0x49]	14458	1		T6	1		T12	3		T35	1
valid_sources[0x4a]	16819	1		T15	296		T17	1		T18	140
valid_sources[0x4b]	15507	1		T9	2		T12	1		T15	204
valid_sources[0x4c]	14303	1		T1	1		T15	295		T17	2
valid_sources[0x4d]	15262	1		T9	2		T198	1		T15	29
valid_sources[0x4e]	15754	1		T15	268		T17	1		T50	2
valid_sources[0x4f]	14813	1		T1	1		T15	122		T17	1
valid_sources[0x50]	15306	1		T12	1		T15	23		T18	150
valid_sources[0x51]	16658	1		T15	14		T18	168		T19	470
valid_sources[0x52]	14251	1		T1	1		T15	10		T18	170
valid_sources[0x53]	15218	1		T13	1		T15	307		T18	154
valid_sources[0x54]	15195	1		T12	6		T35	3		T15	17
valid_sources[0x55]	17484	1		T9	1		T12	4		T15	198
valid_sources[0x56]	18773	1		T15	274		T18	145		T51	2
valid_sources[0x57]	18463	1		T33	1		T15	222		T18	135
valid_sources[0x58]	16560	1		T15	122		T18	123		T19	348
valid_sources[0x59]	15629	1		T1	3		T8	22		T198	1
valid_sources[0x5a]	18802	1		T15	263		T18	127		T19	883
valid_sources[0x5b]	14439	1		T13	2		T15	139		T48	1
valid_sources[0x5c]	17217	1		T6	1		T15	446		T18	144
valid_sources[0x5d]	16130	1		T35	1		T15	16		T18	150
valid_sources[0x5e]	16182	1		T12	3		T14	5		T15	230
valid_sources[0x5f]	15399	1		T6	1		T12	4		T15	320
valid_sources[0x60]	16135	1		T6	1		T15	339		T18	153
valid_sources[0x61]	16398	1		T9	1		T15	175		T18	149
valid_sources[0x62]	15927	1		T15	202		T18	139		T19	451
valid_sources[0x63]	16256	1		T12	7		T15	38		T18	149
valid_sources[0x64]	16379	1		T7	1		T15	9		T18	169
valid_sources[0x65]	16168	1		T15	258		T18	127		T19	280
valid_sources[0x66]	15271	1		T12	1		T15	22		T18	154
valid_sources[0x67]	16890	1		T1	1		T12	2		T15	25
valid_sources[0x68]	17746	1		T12	5		T15	165		T18	142
valid_sources[0x69]	14872	1		T7	1		T15	6		T18	171
valid_sources[0x6a]	16436	1		T15	185		T18	164		T19	420
valid_sources[0x6b]	17155	1		T33	1		T15	24		T18	123
valid_sources[0x6c]	16955	1		T15	212		T18	140		T19	546
valid_sources[0x6d]	15286	1		T198	1		T15	175		T18	151
valid_sources[0x6e]	16304	1		T6	3		T12	1		T15	21
valid_sources[0x6f]	17164	1		T1	2		T12	1		T15	517
valid_sources[0x70]	15957	1		T35	1		T15	12		T18	118
valid_sources[0x71]	15434	1		T33	1		T15	94		T18	147
valid_sources[0x72]	15319	1		T12	5		T13	1		T199	1
valid_sources[0x73]	17181	1		T5	2		T12	1		T15	194
valid_sources[0x74]	15314	1		T7	1		T15	192		T18	142
valid_sources[0x75]	15740	1		T12	2		T198	1		T15	147
valid_sources[0x76]	16094	1		T35	1		T15	210		T18	139
valid_sources[0x77]	15886	1		T12	1		T33	1		T15	325
valid_sources[0x78]	16096	1		T12	2		T15	112		T18	143
valid_sources[0x79]	15412	1		T12	2		T15	191		T18	137
valid_sources[0x7a]	17048	1		T6	1		T15	409		T18	136
valid_sources[0x7b]	16006	1		T12	4		T198	1		T199	1
valid_sources[0x7c]	16495	1		T15	233		T18	143		T19	690
valid_sources[0x7d]	17688	1		T12	1		T15	128		T18	168
valid_sources[0x7e]	15083	1		T7	1		T15	47		T18	140
valid_sources[0x7f]	15426	1		T9	1		T12	3		T14	4
valid_sources[0x80]	15960	1		T15	4		T18	161		T19	329

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

943330

1

T3

15

T4

17

T6

1

values[0x0]

all_enables

biggest_size

1419967

1

T1

8

T2

8

T3

101

values[0x1]

all_enables

biggest_size

1419172

1

T1

8

T2

5

T3

119