Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	872561180	4540759	0	0
wdog_bark_thold_rd_A	872561180	55349	0	0
wdog_bite_thold_rd_A	872561180	48912	0	0
wdog_ctrl_rd_A	872561180	48738	0	0
wdog_regwen_rd_A	872561180	55742	0	0
wkup_ctrl_rd_A	872561180	49008	0	0
wkup_thold_hi_rd_A	872561180	55960	0	0
wkup_thold_lo_rd_A	872561180	48380	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872561180	4540759	0	0
T15	187405	39327	0	0
T16	388832	0	0	0
T17	2785	0	0	0
T18	172777	39718	0	0
T19	247096	91694	0	0
T26	0	56736	0	0
T34	48397	0	0	0
T42	0	99579	0	0
T43	0	79595	0	0
T44	0	116484	0	0
T45	0	239718	0	0
T46	0	92283	0	0
T47	0	85706	0	0
T48	386554	0	0	0
T49	16700	0	0	0
T50	34486	0	0	0
T51	10536	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872561180	55349	0	0
T15	187405	3940	0	0
T16	388832	0	0	0
T17	2785	0	0	0
T18	172777	2064	0	0
T19	247096	0	0	0
T26	0	6098	0	0
T34	48397	0	0	0
T47	0	8044	0	0
T48	386554	0	0	0
T49	16700	0	0	0
T50	34486	0	0	0
T51	10536	0	0	0
T90	0	7141	0	0
T91	0	5742	0	0
T92	0	6082	0	0
T93	0	12925	0	0
T94	0	2298	0	0
T95	0	28	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872561180	48912	0	0
T15	187405	3600	0	0
T16	388832	0	0	0
T17	2785	0	0	0
T18	172777	1835	0	0
T19	247096	0	0	0
T26	0	5038	0	0
T34	48397	0	0	0
T47	0	7336	0	0
T48	386554	0	0	0
T49	16700	0	0	0
T50	34486	0	0	0
T51	10536	0	0	0
T90	0	6257	0	0
T91	0	4836	0	0
T92	0	5894	0	0
T93	0	11121	0	0
T94	0	2012	0	0
T95	0	6	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872561180	48738	0	0
T15	187405	3322	0	0
T16	388832	0	0	0
T17	2785	0	0	0
T18	172777	1899	0	0
T19	247096	0	0	0
T26	0	5310	0	0
T34	48397	0	0	0
T47	0	7242	0	0
T48	386554	0	0	0
T49	16700	0	0	0
T50	34486	0	0	0
T51	10536	0	0	0
T90	0	6166	0	0
T91	0	4974	0	0
T92	0	5604	0	0
T93	0	11043	0	0
T94	0	2053	0	0
T95	0	5	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872561180	55742	0	0
T15	187405	3798	0	0
T16	388832	0	0	0
T17	2785	0	0	0
T18	172777	2228	0	0
T19	247096	0	0	0
T26	0	5880	0	0
T34	48397	0	0	0
T47	0	8126	0	0
T48	386554	0	0	0
T49	16700	0	0	0
T50	34486	0	0	0
T51	10536	0	0	0
T90	0	7336	0	0
T91	0	5574	0	0
T92	0	6385	0	0
T93	0	12903	0	0
T94	0	2291	0	0
T95	0	23	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872561180	49008	0	0
T15	187405	3607	0	0
T16	388832	0	0	0
T17	2785	0	0	0
T18	172777	1862	0	0
T19	247096	0	0	0
T26	0	4983	0	0
T34	48397	0	0	0
T47	0	7085	0	0
T48	386554	0	0	0
T49	16700	0	0	0
T50	34486	0	0	0
T51	10536	0	0	0
T90	0	6200	0	0
T91	0	5365	0	0
T92	0	5681	0	0
T93	0	11201	0	0
T94	0	1915	0	0
T95	0	14	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872561180	55960	0	0
T15	187405	3793	0	0
T16	388832	0	0	0
T17	2785	0	0	0
T18	172777	2349	0	0
T19	247096	0	0	0
T26	0	5760	0	0
T34	48397	0	0	0
T47	0	7830	0	0
T48	386554	0	0	0
T49	16700	0	0	0
T50	34486	0	0	0
T51	10536	0	0	0
T90	0	7391	0	0
T91	0	5504	0	0
T92	0	6700	0	0
T93	0	13322	0	0
T94	0	2266	0	0
T95	0	3	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872561180	48380	0	0
T15	187405	3189	0	0
T16	388832	0	0	0
T17	2785	0	0	0
T18	172777	1848	0	0
T19	247096	0	0	0
T26	0	4856	0	0
T34	48397	0	0	0
T47	0	7053	0	0
T48	386554	0	0	0
T49	16700	0	0	0
T50	34486	0	0	0
T51	10536	0	0	0
T90	0	6072	0	0
T91	0	5000	0	0
T92	0	5711	0	0
T93	0	11568	0	0
T94	0	1977	0	0
T95	0	20	0	0