Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	350292	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4253142	1		T1	13		T2	12		T3	103400

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1132287	1		T1	1		T2	1		T3	27345
values[0x0]	1625888	1		T1	11		T2	7		T3	39566
values[0x1]	1845259	1		T1	7		T2	12		T3	44590

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156699	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4446735	1		T1	14		T2	14		T3	107993

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18658	1		T2	1		T3	452		T5	761
valid_sources[0x01]	18914	1		T3	425		T5	794		T6	400
valid_sources[0x02]	16597	1		T3	441		T5	497		T6	302
valid_sources[0x03]	16688	1		T3	419		T5	558		T6	387
valid_sources[0x04]	19007	1		T3	454		T5	688		T6	421
valid_sources[0x05]	19884	1		T3	434		T5	533		T6	346
valid_sources[0x06]	17079	1		T3	425		T5	642		T6	354
valid_sources[0x07]	19698	1		T3	431		T5	687		T6	479
valid_sources[0x08]	17659	1		T3	451		T5	730		T6	455
valid_sources[0x09]	17904	1		T3	432		T5	785		T6	368
valid_sources[0x0a]	18063	1		T3	424		T5	625		T6	435
valid_sources[0x0b]	16554	1		T3	431		T5	368		T6	413
valid_sources[0x0c]	17688	1		T1	1		T3	420		T5	801
valid_sources[0x0d]	18031	1		T3	447		T5	465		T6	501
valid_sources[0x0e]	17537	1		T2	1		T3	470		T5	658
valid_sources[0x0f]	17441	1		T3	431		T5	639		T6	336
valid_sources[0x10]	16824	1		T3	440		T5	490		T6	365
valid_sources[0x11]	16485	1		T3	462		T5	697		T6	411
valid_sources[0x12]	18192	1		T3	427		T5	569		T6	402
valid_sources[0x13]	18683	1		T3	451		T5	878		T6	344
valid_sources[0x14]	18249	1		T3	502		T5	726		T6	401
valid_sources[0x15]	18309	1		T3	482		T5	789		T6	453
valid_sources[0x16]	17995	1		T1	1		T3	418		T5	753
valid_sources[0x17]	17911	1		T3	473		T5	523		T6	341
valid_sources[0x18]	16860	1		T3	418		T5	560		T6	376
valid_sources[0x19]	18047	1		T3	411		T5	460		T6	415
valid_sources[0x1a]	17194	1		T3	423		T5	658		T6	389
valid_sources[0x1b]	17134	1		T3	425		T5	647		T6	346
valid_sources[0x1c]	18523	1		T3	426		T5	426		T6	427
valid_sources[0x1d]	18279	1		T3	443		T5	705		T6	401
valid_sources[0x1e]	17954	1		T3	445		T5	565		T6	421
valid_sources[0x1f]	17323	1		T3	449		T5	553		T6	414
valid_sources[0x20]	17978	1		T3	447		T5	440		T6	390
valid_sources[0x21]	18680	1		T3	424		T5	724		T6	364
valid_sources[0x22]	18301	1		T3	445		T5	620		T6	396
valid_sources[0x23]	17841	1		T3	493		T5	686		T6	465
valid_sources[0x24]	16840	1		T3	366		T5	734		T6	377
valid_sources[0x25]	17121	1		T3	457		T5	589		T6	385
valid_sources[0x26]	18730	1		T3	409		T5	737		T6	387
valid_sources[0x27]	16750	1		T3	437		T5	475		T6	452
valid_sources[0x28]	16990	1		T3	425		T5	483		T6	465
valid_sources[0x29]	18371	1		T3	385		T5	539		T6	480
valid_sources[0x2a]	17447	1		T3	408		T5	645		T6	352
valid_sources[0x2b]	18295	1		T2	1		T3	421		T5	686
valid_sources[0x2c]	18433	1		T3	394		T5	750		T6	421
valid_sources[0x2d]	17721	1		T3	455		T5	516		T6	444
valid_sources[0x2e]	17832	1		T3	448		T5	660		T6	317
valid_sources[0x2f]	17516	1		T3	438		T5	744		T6	404
valid_sources[0x30]	18000	1		T2	1		T3	426		T5	760
valid_sources[0x31]	19563	1		T3	447		T5	419		T6	419
valid_sources[0x32]	18561	1		T3	479		T5	766		T6	495
valid_sources[0x33]	18419	1		T2	1		T3	443		T5	849
valid_sources[0x34]	18284	1		T1	1		T3	441		T5	425
valid_sources[0x35]	18799	1		T3	429		T5	817		T6	371
valid_sources[0x36]	17128	1		T3	435		T5	804		T6	410
valid_sources[0x37]	20023	1		T3	445		T5	703		T6	440
valid_sources[0x38]	19863	1		T3	442		T5	645		T6	327
valid_sources[0x39]	17044	1		T3	462		T5	427		T6	398
valid_sources[0x3a]	17591	1		T3	415		T5	586		T6	403
valid_sources[0x3b]	18424	1		T3	467		T5	606		T6	387
valid_sources[0x3c]	17162	1		T3	435		T5	724		T6	405
valid_sources[0x3d]	19083	1		T3	423		T5	829		T6	383
valid_sources[0x3e]	18022	1		T3	426		T5	544		T6	387
valid_sources[0x3f]	15981	1		T3	415		T5	604		T6	371
valid_sources[0x40]	15437	1		T3	450		T5	513		T6	432
valid_sources[0x41]	17790	1		T3	403		T5	753		T6	348
valid_sources[0x42]	18553	1		T3	484		T5	787		T6	389
valid_sources[0x43]	18952	1		T3	459		T5	599		T6	512
valid_sources[0x44]	17123	1		T3	426		T5	739		T6	372
valid_sources[0x45]	18084	1		T3	433		T5	764		T6	411
valid_sources[0x46]	18061	1		T2	1		T3	438		T5	564
valid_sources[0x47]	16431	1		T3	409		T5	670		T6	479
valid_sources[0x48]	17975	1		T3	474		T5	688		T6	347
valid_sources[0x49]	17075	1		T3	432		T5	650		T6	346
valid_sources[0x4a]	18544	1		T3	393		T5	581		T6	410
valid_sources[0x4b]	17177	1		T3	438		T5	622		T6	315
valid_sources[0x4c]	18070	1		T3	471		T5	563		T6	343
valid_sources[0x4d]	19566	1		T3	448		T5	660		T6	420
valid_sources[0x4e]	17169	1		T3	408		T5	740		T6	423
valid_sources[0x4f]	17257	1		T2	1		T3	431		T5	774
valid_sources[0x50]	17185	1		T3	414		T5	567		T6	339
valid_sources[0x51]	19107	1		T3	445		T5	613		T6	465
valid_sources[0x52]	19763	1		T3	424		T5	566		T6	448
valid_sources[0x53]	18591	1		T3	406		T5	459		T6	408
valid_sources[0x54]	19516	1		T3	401		T5	713		T6	371
valid_sources[0x55]	16912	1		T3	392		T5	564		T6	335
valid_sources[0x56]	18232	1		T2	1		T3	471		T5	670
valid_sources[0x57]	20573	1		T3	429		T5	585		T6	356
valid_sources[0x58]	19822	1		T3	453		T5	473		T6	428
valid_sources[0x59]	18492	1		T3	410		T4	1		T5	757
valid_sources[0x5a]	17406	1		T3	489		T5	723		T6	411
valid_sources[0x5b]	18611	1		T3	425		T5	821		T6	413
valid_sources[0x5c]	18103	1		T3	447		T5	569		T6	347
valid_sources[0x5d]	17347	1		T3	417		T5	600		T6	397
valid_sources[0x5e]	18185	1		T3	403		T5	940		T6	401
valid_sources[0x5f]	18152	1		T3	467		T5	795		T6	374
valid_sources[0x60]	17204	1		T3	487		T5	688		T6	355
valid_sources[0x61]	18199	1		T3	433		T4	1		T5	584
valid_sources[0x62]	17008	1		T3	371		T4	1		T5	692
valid_sources[0x63]	18629	1		T3	449		T5	572		T6	422
valid_sources[0x64]	17454	1		T2	1		T3	418		T5	718
valid_sources[0x65]	17593	1		T3	458		T4	3		T5	651
valid_sources[0x66]	18628	1		T3	413		T5	721		T6	354
valid_sources[0x67]	18279	1		T3	459		T5	675		T6	356
valid_sources[0x68]	18434	1		T3	438		T5	619		T6	423
valid_sources[0x69]	18173	1		T1	1		T3	453		T5	358
valid_sources[0x6a]	17333	1		T1	1		T3	427		T5	512
valid_sources[0x6b]	17997	1		T3	397		T4	1		T5	656
valid_sources[0x6c]	18093	1		T3	429		T5	717		T6	340
valid_sources[0x6d]	18223	1		T3	409		T5	586		T6	428
valid_sources[0x6e]	18726	1		T3	468		T5	747		T6	294
valid_sources[0x6f]	19553	1		T3	440		T5	772		T6	462
valid_sources[0x70]	17432	1		T3	403		T5	589		T6	384
valid_sources[0x71]	17137	1		T3	443		T5	538		T6	362
valid_sources[0x72]	17819	1		T3	424		T5	646		T6	361
valid_sources[0x73]	20125	1		T3	476		T5	580		T6	436
valid_sources[0x74]	17039	1		T3	410		T5	404		T6	376
valid_sources[0x75]	18702	1		T3	416		T5	784		T6	394
valid_sources[0x76]	19009	1		T1	1		T3	467		T5	777
valid_sources[0x77]	19857	1		T3	447		T5	603		T6	373
valid_sources[0x78]	19202	1		T3	404		T5	674		T6	391
valid_sources[0x79]	15958	1		T3	426		T5	391		T6	388
valid_sources[0x7a]	18580	1		T3	387		T5	676		T6	397
valid_sources[0x7b]	17558	1		T3	433		T5	651		T6	413
valid_sources[0x7c]	17593	1		T3	445		T5	684		T6	539
valid_sources[0x7d]	18159	1		T3	441		T5	756		T6	432
valid_sources[0x7e]	17420	1		T1	1		T3	454		T4	1
valid_sources[0x7f]	18948	1		T3	474		T5	582		T6	360
valid_sources[0x80]	17780	1		T1	1		T3	416		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1061237

1

T3

25733

T5

37938

T6

23647

values[0x0]

all_enables

biggest_size

1596411

1

T1

7

T2

5

T3

38992

values[0x1]

all_enables

biggest_size

1595494

1

T1

6

T2

7

T3

38675