Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	786077531	5057011	0	0
wdog_bark_thold_rd_A	786077531	122049	0	0
wdog_bite_thold_rd_A	786077531	105491	0	0
wdog_ctrl_rd_A	786077531	107279	0	0
wdog_regwen_rd_A	786077531	122069	0	0
wkup_ctrl_rd_A	786077531	105634	0	0
wkup_thold_hi_rd_A	786077531	121744	0	0
wkup_thold_lo_rd_A	786077531	108304	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786077531	5057011	0	0
T3	332546	125758	0	0
T4	9456	0	0	0
T5	700441	189038	0	0
T6	322777	116436	0	0
T7	50896	0	0	0
T8	40092	0	0	0
T9	10320	0	0	0
T10	121498	0	0	0
T11	5446	0	0	0
T13	0	62213	0	0
T14	54532	0	0	0
T33	0	21511	0	0
T34	0	67530	0	0
T44	0	17806	0	0
T45	0	98604	0	0
T46	0	109948	0	0
T47	0	88571	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786077531	122049	0	0
T45	486347	4982	0	0
T46	387349	0	0	0
T47	400895	8616	0	0
T55	0	12352	0	0
T82	128244	0	0	0
T83	596676	0	0	0
T84	18978	0	0	0
T85	252634	0	0	0
T86	123699	2566	0	0
T87	582353	0	0	0
T88	47650	0	0	0
T89	0	9735	0	0
T94	0	4308	0	0
T95	0	14059	0	0
T96	0	1619	0	0
T97	0	3078	0	0
T98	0	13245	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786077531	105491	0	0
T45	486347	4682	0	0
T46	387349	0	0	0
T47	400895	7468	0	0
T55	0	10396	0	0
T82	128244	0	0	0
T83	596676	0	0	0
T84	18978	0	0	0
T85	252634	0	0	0
T86	123699	2478	0	0
T87	582353	0	0	0
T88	47650	0	0	0
T89	0	8416	0	0
T94	0	3665	0	0
T95	0	11477	0	0
T96	0	1299	0	0
T97	0	2560	0	0
T98	0	11285	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786077531	107279	0	0
T45	486347	4331	0	0
T46	387349	0	0	0
T47	400895	7544	0	0
T55	0	11275	0	0
T82	128244	0	0	0
T83	596676	0	0	0
T84	18978	0	0	0
T85	252634	0	0	0
T86	123699	2657	0	0
T87	582353	0	0	0
T88	47650	0	0	0
T89	0	8581	0	0
T94	0	3636	0	0
T95	0	12028	0	0
T96	0	1241	0	0
T97	0	2775	0	0
T98	0	10997	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786077531	122069	0	0
T45	486347	5100	0	0
T46	387349	0	0	0
T47	400895	8399	0	0
T55	0	12409	0	0
T82	128244	0	0	0
T83	596676	0	0	0
T84	18978	0	0	0
T85	252634	0	0	0
T86	123699	2859	0	0
T87	582353	0	0	0
T88	47650	0	0	0
T89	0	9764	0	0
T94	0	4277	0	0
T95	0	13420	0	0
T96	0	1526	0	0
T97	0	3078	0	0
T98	0	12915	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786077531	105634	0	0
T45	486347	4260	0	0
T46	387349	0	0	0
T47	400895	7548	0	0
T55	0	10614	0	0
T82	128244	0	0	0
T83	596676	0	0	0
T84	18978	0	0	0
T85	252634	0	0	0
T86	123699	2549	0	0
T87	582353	0	0	0
T88	47650	0	0	0
T89	0	8382	0	0
T94	0	3851	0	0
T95	0	11807	0	0
T96	0	1298	0	0
T97	0	2938	0	0
T98	0	11124	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786077531	121744	0	0
T45	486347	5108	0	0
T46	387349	0	0	0
T47	400895	8805	0	0
T55	0	12817	0	0
T82	128244	0	0	0
T83	596676	0	0	0
T84	18978	0	0	0
T85	252634	0	0	0
T86	123699	2734	0	0
T87	582353	0	0	0
T88	47650	0	0	0
T89	0	9448	0	0
T94	0	3867	0	0
T95	0	13535	0	0
T96	0	1562	0	0
T97	0	3083	0	0
T98	0	12569	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786077531	108304	0	0
T45	486347	4375	0	0
T46	387349	0	0	0
T47	400895	7981	0	0
T55	0	10739	0	0
T82	128244	0	0	0
T83	596676	0	0	0
T84	18978	0	0	0
T85	252634	0	0	0
T86	123699	2356	0	0
T87	582353	0	0	0
T88	47650	0	0	0
T89	0	8673	0	0
T94	0	3970	0	0
T95	0	12304	0	0
T96	0	1110	0	0
T97	0	2737	0	0
T98	0	11275	0	0