Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	382524	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4682250	1		T1	15		T2	184		T3	16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1245358	1		T1	1		T2	53		T3	1
values[0x0]	1789054	1		T1	12		T2	121		T3	14
values[0x1]	2030362	1		T1	6		T2	122		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	171180	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4893594	1		T1	16		T2	203		T3	17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19542	1		T5	246		T12	1		T14	74
valid_sources[0x01]	18940	1		T5	192		T6	6		T194	1
valid_sources[0x02]	18484	1		T5	230		T12	4		T14	72
valid_sources[0x03]	18578	1		T5	233		T14	73		T196	1
valid_sources[0x04]	18920	1		T5	246		T14	90		T15	500
valid_sources[0x05]	18103	1		T2	9		T5	215		T14	87
valid_sources[0x06]	19622	1		T5	217		T6	2		T10	2
valid_sources[0x07]	21009	1		T2	7		T5	246		T12	3
valid_sources[0x08]	19471	1		T5	184		T12	8		T14	87
valid_sources[0x09]	19199	1		T2	4		T5	220		T8	1
valid_sources[0x0a]	19366	1		T5	214		T14	100		T15	514
valid_sources[0x0b]	21008	1		T5	222		T6	7		T8	1
valid_sources[0x0c]	18947	1		T5	182		T12	1		T14	104
valid_sources[0x0d]	18543	1		T5	225		T6	4		T12	3
valid_sources[0x0e]	18349	1		T1	9		T5	192		T6	1
valid_sources[0x0f]	20213	1		T5	217		T9	3		T12	9
valid_sources[0x10]	20777	1		T5	226		T14	76		T15	424
valid_sources[0x11]	20178	1		T5	217		T8	1		T14	96
valid_sources[0x12]	20567	1		T5	212		T7	1		T12	5
valid_sources[0x13]	20714	1		T5	217		T194	1		T14	91
valid_sources[0x14]	20493	1		T5	219		T14	95		T15	534
valid_sources[0x15]	18257	1		T5	223		T14	102		T15	519
valid_sources[0x16]	20312	1		T5	223		T9	1		T12	3
valid_sources[0x17]	19313	1		T2	3		T5	230		T6	7
valid_sources[0x18]	18948	1		T2	21		T5	226		T14	98
valid_sources[0x19]	18617	1		T5	239		T12	3		T14	79
valid_sources[0x1a]	21763	1		T5	221		T9	1		T14	102
valid_sources[0x1b]	20125	1		T5	206		T6	2		T7	1
valid_sources[0x1c]	19568	1		T5	230		T6	1		T12	2
valid_sources[0x1d]	18739	1		T5	217		T14	75		T15	526
valid_sources[0x1e]	19632	1		T5	237		T6	5		T12	9
valid_sources[0x1f]	20581	1		T5	211		T14	88		T15	496
valid_sources[0x20]	19331	1		T1	3		T5	215		T12	6
valid_sources[0x21]	18371	1		T5	210		T12	5		T14	90
valid_sources[0x22]	18626	1		T5	205		T14	111		T196	1
valid_sources[0x23]	18154	1		T5	219		T6	4		T12	1
valid_sources[0x24]	18821	1		T5	210		T6	5		T194	1
valid_sources[0x25]	20138	1		T5	218		T12	2		T14	106
valid_sources[0x26]	19659	1		T5	223		T12	1		T14	91
valid_sources[0x27]	19080	1		T5	223		T6	16		T11	1
valid_sources[0x28]	20634	1		T5	224		T9	1		T12	4
valid_sources[0x29]	21198	1		T2	3		T5	229		T14	98
valid_sources[0x2a]	19583	1		T2	11		T5	240		T194	2
valid_sources[0x2b]	19793	1		T5	221		T7	1		T8	1
valid_sources[0x2c]	18924	1		T2	33		T5	199		T14	88
valid_sources[0x2d]	20029	1		T5	212		T6	1		T8	1
valid_sources[0x2e]	20985	1		T5	206		T12	1		T14	95
valid_sources[0x2f]	20103	1		T5	208		T14	88		T15	506
valid_sources[0x30]	19740	1		T5	218		T14	97		T15	490
valid_sources[0x31]	19926	1		T4	369		T5	215		T14	79
valid_sources[0x32]	17587	1		T5	253		T8	1		T12	1
valid_sources[0x33]	19655	1		T5	232		T7	1		T11	1
valid_sources[0x34]	20252	1		T5	208		T11	1		T12	1
valid_sources[0x35]	19052	1		T5	242		T13	2		T14	112
valid_sources[0x36]	19647	1		T5	218		T6	2		T13	1
valid_sources[0x37]	21240	1		T5	204		T11	1		T12	2
valid_sources[0x38]	20011	1		T5	218		T12	5		T14	87
valid_sources[0x39]	17943	1		T5	226		T6	5		T43	1
valid_sources[0x3a]	19170	1		T2	4		T5	208		T6	5
valid_sources[0x3b]	21443	1		T5	248		T6	10		T14	97
valid_sources[0x3c]	19783	1		T5	222		T12	1		T14	75
valid_sources[0x3d]	20782	1		T5	201		T14	74		T15	521
valid_sources[0x3e]	19435	1		T5	226		T12	3		T14	80
valid_sources[0x3f]	20229	1		T5	217		T32	22		T14	89
valid_sources[0x40]	21031	1		T5	237		T14	77		T15	505
valid_sources[0x41]	19347	1		T5	218		T6	1		T12	2
valid_sources[0x42]	20390	1		T5	207		T12	2		T43	1
valid_sources[0x43]	20939	1		T5	221		T8	1		T14	89
valid_sources[0x44]	21004	1		T5	204		T7	1		T12	3
valid_sources[0x45]	20449	1		T5	228		T12	3		T14	104
valid_sources[0x46]	19067	1		T5	224		T10	3		T12	3
valid_sources[0x47]	18333	1		T5	230		T8	1		T43	1
valid_sources[0x48]	21166	1		T5	220		T6	1		T12	6
valid_sources[0x49]	20531	1		T5	197		T14	82		T15	519
valid_sources[0x4a]	19848	1		T5	203		T14	82		T15	500
valid_sources[0x4b]	20636	1		T5	208		T6	3		T12	3
valid_sources[0x4c]	19933	1		T5	236		T14	93		T15	530
valid_sources[0x4d]	22279	1		T5	241		T14	101		T15	465
valid_sources[0x4e]	17564	1		T5	190		T14	90		T15	519
valid_sources[0x4f]	20200	1		T5	210		T14	89		T15	521
valid_sources[0x50]	20491	1		T2	8		T5	236		T14	91
valid_sources[0x51]	19488	1		T5	222		T14	92		T15	486
valid_sources[0x52]	21026	1		T5	202		T11	1		T12	1
valid_sources[0x53]	20265	1		T5	220		T6	3		T9	1
valid_sources[0x54]	19269	1		T2	10		T5	221		T6	2
valid_sources[0x55]	18513	1		T5	210		T14	81		T15	535
valid_sources[0x56]	19112	1		T5	243		T6	6		T12	1
valid_sources[0x57]	19664	1		T5	215		T12	4		T14	74
valid_sources[0x58]	20322	1		T2	16		T5	208		T14	96
valid_sources[0x59]	18666	1		T5	225		T14	75		T15	489
valid_sources[0x5a]	21645	1		T5	237		T12	4		T14	91
valid_sources[0x5b]	18882	1		T5	204		T12	1		T14	73
valid_sources[0x5c]	20167	1		T5	210		T12	4		T14	101
valid_sources[0x5d]	19967	1		T5	210		T14	89		T15	546
valid_sources[0x5e]	18700	1		T5	202		T7	1		T12	1
valid_sources[0x5f]	20441	1		T5	196		T14	75		T15	545
valid_sources[0x60]	20858	1		T5	234		T6	2		T14	82
valid_sources[0x61]	19139	1		T5	208		T14	97		T15	574
valid_sources[0x62]	19820	1		T5	192		T194	1		T14	86
valid_sources[0x63]	20308	1		T5	226		T9	3		T12	6
valid_sources[0x64]	18956	1		T5	239		T12	4		T14	70
valid_sources[0x65]	20763	1		T5	221		T14	76		T15	528
valid_sources[0x66]	22259	1		T5	220		T6	3		T14	78
valid_sources[0x67]	20206	1		T5	227		T13	1		T14	65
valid_sources[0x68]	20769	1		T5	235		T11	1		T14	93
valid_sources[0x69]	18580	1		T5	213		T6	16		T14	86
valid_sources[0x6a]	18612	1		T5	220		T8	1		T14	87
valid_sources[0x6b]	20476	1		T5	208		T12	4		T43	1
valid_sources[0x6c]	18508	1		T5	204		T14	96		T15	499
valid_sources[0x6d]	21762	1		T5	230		T13	1		T14	84
valid_sources[0x6e]	18592	1		T5	210		T6	6		T43	1
valid_sources[0x6f]	20538	1		T5	237		T194	1		T14	79
valid_sources[0x70]	19590	1		T5	227		T14	95		T15	531
valid_sources[0x71]	20796	1		T5	240		T14	108		T196	1
valid_sources[0x72]	19685	1		T2	2		T5	201		T6	1
valid_sources[0x73]	19835	1		T5	210		T14	85		T15	466
valid_sources[0x74]	20303	1		T5	210		T12	5		T14	91
valid_sources[0x75]	20338	1		T2	2		T5	213		T13	1
valid_sources[0x76]	20814	1		T5	230		T6	1		T194	2
valid_sources[0x77]	18961	1		T5	225		T7	1		T12	5
valid_sources[0x78]	19391	1		T5	227		T14	111		T15	508
valid_sources[0x79]	19457	1		T5	191		T9	1		T12	4
valid_sources[0x7a]	19543	1		T5	231		T8	2		T12	3
valid_sources[0x7b]	19201	1		T5	220		T14	93		T15	448
valid_sources[0x7c]	20715	1		T5	222		T12	6		T14	86
valid_sources[0x7d]	20468	1		T5	209		T12	4		T14	94
valid_sources[0x7e]	19114	1		T5	210		T10	2		T11	1
valid_sources[0x7f]	19653	1		T1	1		T5	232		T8	1
valid_sources[0x80]	20085	1		T5	220		T12	5		T14	87

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1168194

1

T2

31

T3

1

T4

20

values[0x0]

all_enables

biggest_size

1756584

1

T1

12

T2

83

T3

9

values[0x1]

all_enables

biggest_size

1757472

1

T1

3

T2

70

T3

6