Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	802461831	5544644	0	0
wdog_bark_thold_rd_A	802461831	138435	0	0
wdog_bite_thold_rd_A	802461831	122456	0	0
wdog_ctrl_rd_A	802461831	121215	0	0
wdog_regwen_rd_A	802461831	139235	0	0
wkup_ctrl_rd_A	802461831	120237	0	0
wkup_thold_hi_rd_A	802461831	138796	0	0
wkup_thold_lo_rd_A	802461831	121814	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802461831	5544644	0	0
T5	236999	56583	0	0
T6	797894	0	0	0
T7	10521	0	0	0
T8	630427	0	0	0
T9	10421	0	0	0
T10	40616	0	0	0
T11	442250	0	0	0
T12	169986	0	0	0
T14	0	23224	0	0
T15	0	141420	0	0
T22	0	30685	0	0
T24	0	147481	0	0
T29	0	145798	0	0
T31	0	51995	0	0
T32	41469	0	0	0
T40	0	224328	0	0
T41	0	68223	0	0
T42	0	366653	0	0
T43	421212	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802461831	138435	0	0
T5	236999	3227	0	0
T6	797894	0	0	0
T7	10521	0	0	0
T8	630427	0	0	0
T9	10421	0	0	0
T10	40616	0	0	0
T11	442250	0	0	0
T12	169986	0	0	0
T14	0	2312	0	0
T15	0	13595	0	0
T31	0	5141	0	0
T32	41469	0	0	0
T43	421212	0	0	0
T54	0	14011	0	0
T80	0	7943	0	0
T81	0	2652	0	0
T82	0	6258	0	0
T83	0	12029	0	0
T84	0	9454	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802461831	122456	0	0
T5	236999	2821	0	0
T6	797894	0	0	0
T7	10521	0	0	0
T8	630427	0	0	0
T9	10421	0	0	0
T10	40616	0	0	0
T11	442250	0	0	0
T12	169986	0	0	0
T14	0	1899	0	0
T15	0	12750	0	0
T31	0	4649	0	0
T32	41469	0	0	0
T43	421212	0	0	0
T54	0	11994	0	0
T80	0	6994	0	0
T81	0	2340	0	0
T82	0	5575	0	0
T83	0	10873	0	0
T84	0	8298	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802461831	121215	0	0
T5	236999	2865	0	0
T6	797894	0	0	0
T7	10521	0	0	0
T8	630427	0	0	0
T9	10421	0	0	0
T10	40616	0	0	0
T11	442250	0	0	0
T12	169986	0	0	0
T14	0	1995	0	0
T15	0	12380	0	0
T31	0	4508	0	0
T32	41469	0	0	0
T43	421212	0	0	0
T54	0	11947	0	0
T80	0	6879	0	0
T81	0	2520	0	0
T82	0	5276	0	0
T83	0	10847	0	0
T84	0	8461	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802461831	139235	0	0
T5	236999	3601	0	0
T6	797894	0	0	0
T7	10521	0	0	0
T8	630427	0	0	0
T9	10421	0	0	0
T10	40616	0	0	0
T11	442250	0	0	0
T12	169986	0	0	0
T14	0	2350	0	0
T15	0	13962	0	0
T31	0	5072	0	0
T32	41469	0	0	0
T43	421212	0	0	0
T54	0	13501	0	0
T80	0	7561	0	0
T81	0	2730	0	0
T82	0	5914	0	0
T83	0	12721	0	0
T84	0	9755	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802461831	120237	0	0
T5	236999	2826	0	0
T6	797894	0	0	0
T7	10521	0	0	0
T8	630427	0	0	0
T9	10421	0	0	0
T10	40616	0	0	0
T11	442250	0	0	0
T12	169986	0	0	0
T14	0	1973	0	0
T15	0	12171	0	0
T31	0	4341	0	0
T32	41469	0	0	0
T43	421212	0	0	0
T54	0	11775	0	0
T80	0	7166	0	0
T81	0	2279	0	0
T82	0	5143	0	0
T83	0	10425	0	0
T84	0	8308	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802461831	138796	0	0
T5	236999	3662	0	0
T6	797894	0	0	0
T7	10521	0	0	0
T8	630427	0	0	0
T9	10421	0	0	0
T10	40616	0	0	0
T11	442250	0	0	0
T12	169986	0	0	0
T14	0	2320	0	0
T15	0	13975	0	0
T31	0	5272	0	0
T32	41469	0	0	0
T43	421212	0	0	0
T54	0	14204	0	0
T80	0	7981	0	0
T81	0	2557	0	0
T82	0	5880	0	0
T83	0	12143	0	0
T84	0	9957	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802461831	121814	0	0
T5	236999	2868	0	0
T6	797894	0	0	0
T7	10521	0	0	0
T8	630427	0	0	0
T9	10421	0	0	0
T10	40616	0	0	0
T11	442250	0	0	0
T12	169986	0	0	0
T14	0	2205	0	0
T15	0	12372	0	0
T31	0	4304	0	0
T32	41469	0	0	0
T43	421212	0	0	0
T54	0	11662	0	0
T80	0	6990	0	0
T81	0	2539	0	0
T82	0	5323	0	0
T83	0	11066	0	0
T84	0	8319	0	0