Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	465200	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5815464	1		T1	13		T2	242		T3	13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1544127	1		T1	1		T2	51		T3	1
values[0x0]	2221599	1		T1	9		T2	162		T3	10
values[0x1]	2514938	1		T1	9		T2	170		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204131	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	6076533	1		T1	15		T2	279		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24164	1		T4	224		T9	172		T12	502
valid_sources[0x01]	24388	1		T4	265		T9	186		T11	3
valid_sources[0x02]	24578	1		T4	243		T9	601		T12	498
valid_sources[0x03]	24910	1		T4	240		T9	695		T12	530
valid_sources[0x04]	24555	1		T4	258		T5	1		T9	16
valid_sources[0x05]	25850	1		T4	226		T9	233		T12	513
valid_sources[0x06]	24904	1		T4	257		T9	285		T11	4
valid_sources[0x07]	26158	1		T4	236		T9	395		T12	575
valid_sources[0x08]	24112	1		T4	219		T9	261		T12	506
valid_sources[0x09]	23563	1		T4	262		T9	145		T12	586
valid_sources[0x0a]	25970	1		T4	231		T9	553		T11	6
valid_sources[0x0b]	24879	1		T4	216		T5	1		T9	220
valid_sources[0x0c]	25591	1		T4	220		T9	18		T12	519
valid_sources[0x0d]	25616	1		T4	239		T9	281		T12	562
valid_sources[0x0e]	23131	1		T4	260		T9	330		T12	557
valid_sources[0x0f]	26463	1		T4	249		T9	452		T12	554
valid_sources[0x10]	25878	1		T4	248		T9	474		T11	6
valid_sources[0x11]	24832	1		T4	196		T9	346		T11	14
valid_sources[0x12]	25482	1		T4	223		T9	312		T12	495
valid_sources[0x13]	23647	1		T4	203		T9	189		T12	538
valid_sources[0x14]	24612	1		T4	227		T9	139		T12	478
valid_sources[0x15]	26181	1		T4	219		T9	337		T12	537
valid_sources[0x16]	24607	1		T1	1		T4	223		T9	410
valid_sources[0x17]	23351	1		T4	230		T9	436		T12	516
valid_sources[0x18]	25284	1		T1	1		T4	222		T9	494
valid_sources[0x19]	26313	1		T4	206		T9	337		T12	515
valid_sources[0x1a]	22712	1		T4	224		T5	1		T9	129
valid_sources[0x1b]	24096	1		T4	236		T7	6		T9	121
valid_sources[0x1c]	25801	1		T1	1		T4	217		T9	114
valid_sources[0x1d]	26199	1		T4	237		T5	1		T9	478
valid_sources[0x1e]	24808	1		T4	232		T9	290		T12	556
valid_sources[0x1f]	24215	1		T4	254		T9	780		T10	1
valid_sources[0x20]	23763	1		T4	239		T9	51		T12	543
valid_sources[0x21]	24983	1		T4	202		T9	525		T11	2
valid_sources[0x22]	22761	1		T1	1		T4	235		T9	398
valid_sources[0x23]	25492	1		T4	229		T9	550		T12	545
valid_sources[0x24]	23466	1		T4	222		T9	195		T12	498
valid_sources[0x25]	22594	1		T4	253		T9	359		T12	524
valid_sources[0x26]	26154	1		T4	251		T9	618		T11	5
valid_sources[0x27]	24734	1		T4	215		T9	648		T12	514
valid_sources[0x28]	24984	1		T4	214		T9	651		T12	519
valid_sources[0x29]	24004	1		T4	215		T9	305		T12	536
valid_sources[0x2a]	24186	1		T4	243		T9	277		T12	512
valid_sources[0x2b]	23722	1		T4	258		T6	5		T9	423
valid_sources[0x2c]	24517	1		T1	1		T4	231		T9	478
valid_sources[0x2d]	24950	1		T4	239		T9	737		T12	498
valid_sources[0x2e]	23892	1		T4	229		T9	578		T12	557
valid_sources[0x2f]	24731	1		T4	247		T9	197		T10	2
valid_sources[0x30]	25430	1		T4	239		T9	411		T12	560
valid_sources[0x31]	25600	1		T4	223		T9	321		T11	7
valid_sources[0x32]	24036	1		T4	223		T9	410		T12	511
valid_sources[0x33]	23993	1		T4	264		T9	343		T12	522
valid_sources[0x34]	24784	1		T4	232		T9	361		T11	8
valid_sources[0x35]	24945	1		T4	223		T9	191		T12	571
valid_sources[0x36]	24803	1		T4	221		T9	446		T12	497
valid_sources[0x37]	23904	1		T4	255		T9	557		T11	4
valid_sources[0x38]	25447	1		T1	1		T4	238		T9	230
valid_sources[0x39]	25223	1		T4	200		T9	334		T12	582
valid_sources[0x3a]	23418	1		T4	206		T9	470		T12	485
valid_sources[0x3b]	23137	1		T4	240		T9	308		T11	3
valid_sources[0x3c]	25624	1		T4	250		T9	515		T12	607
valid_sources[0x3d]	24896	1		T4	229		T9	93		T11	7
valid_sources[0x3e]	23745	1		T4	224		T9	413		T12	525
valid_sources[0x3f]	24727	1		T4	237		T9	286		T12	503
valid_sources[0x40]	24123	1		T4	245		T9	253		T12	512
valid_sources[0x41]	23248	1		T4	245		T6	1		T9	67
valid_sources[0x42]	23761	1		T4	254		T9	141		T12	545
valid_sources[0x43]	24099	1		T4	226		T9	117		T11	1
valid_sources[0x44]	23717	1		T4	238		T9	304		T12	535
valid_sources[0x45]	24234	1		T4	265		T9	234		T12	604
valid_sources[0x46]	23396	1		T4	244		T9	533		T12	539
valid_sources[0x47]	24719	1		T4	251		T9	322		T12	498
valid_sources[0x48]	25982	1		T4	232		T9	1252		T12	559
valid_sources[0x49]	25246	1		T4	235		T9	642		T12	500
valid_sources[0x4a]	24287	1		T4	261		T9	27		T11	4
valid_sources[0x4b]	24751	1		T4	219		T9	1144		T12	531
valid_sources[0x4c]	26070	1		T4	235		T9	434		T12	527
valid_sources[0x4d]	22577	1		T4	211		T9	291		T12	517
valid_sources[0x4e]	24062	1		T4	259		T9	419		T12	479
valid_sources[0x4f]	25728	1		T4	205		T9	517		T12	537
valid_sources[0x50]	26675	1		T4	215		T9	470		T11	1
valid_sources[0x51]	24879	1		T4	233		T9	341		T12	511
valid_sources[0x52]	25142	1		T4	246		T9	302		T12	547
valid_sources[0x53]	24886	1		T4	213		T9	285		T12	538
valid_sources[0x54]	22541	1		T4	240		T9	343		T12	547
valid_sources[0x55]	24376	1		T4	243		T9	186		T12	578
valid_sources[0x56]	24879	1		T4	280		T9	336		T12	538
valid_sources[0x57]	23474	1		T4	209		T9	465		T12	542
valid_sources[0x58]	26121	1		T4	255		T9	473		T11	6
valid_sources[0x59]	23958	1		T4	220		T9	46		T12	519
valid_sources[0x5a]	24362	1		T3	13		T4	200		T9	60
valid_sources[0x5b]	23664	1		T4	248		T5	1		T9	758
valid_sources[0x5c]	22806	1		T4	222		T9	386		T11	2
valid_sources[0x5d]	25974	1		T4	254		T9	364		T12	524
valid_sources[0x5e]	25237	1		T4	225		T9	563		T12	553
valid_sources[0x5f]	25598	1		T4	228		T9	397		T12	493
valid_sources[0x60]	23739	1		T4	205		T9	478		T12	557
valid_sources[0x61]	24441	1		T4	227		T9	965		T12	532
valid_sources[0x62]	22087	1		T4	211		T9	161		T12	514
valid_sources[0x63]	25812	1		T4	222		T9	284		T12	534
valid_sources[0x64]	25849	1		T4	218		T7	4		T9	96
valid_sources[0x65]	25368	1		T4	253		T9	231		T12	500
valid_sources[0x66]	26022	1		T4	209		T9	826		T12	505
valid_sources[0x67]	24595	1		T4	257		T9	102		T11	1
valid_sources[0x68]	25235	1		T4	282		T5	2		T9	515
valid_sources[0x69]	25487	1		T4	212		T9	210		T12	531
valid_sources[0x6a]	22982	1		T4	227		T7	2		T9	295
valid_sources[0x6b]	24248	1		T4	227		T6	3		T9	319
valid_sources[0x6c]	24058	1		T4	237		T9	328		T12	606
valid_sources[0x6d]	23021	1		T1	1		T4	268		T9	281
valid_sources[0x6e]	24445	1		T1	1		T4	246		T9	293
valid_sources[0x6f]	24936	1		T1	1		T4	217		T9	151
valid_sources[0x70]	24278	1		T4	225		T9	498		T12	562
valid_sources[0x71]	23906	1		T4	234		T9	367		T12	526
valid_sources[0x72]	23494	1		T4	227		T9	218		T12	563
valid_sources[0x73]	24863	1		T4	247		T9	238		T12	518
valid_sources[0x74]	24576	1		T4	237		T9	412		T12	617
valid_sources[0x75]	23336	1		T4	254		T6	3		T9	43
valid_sources[0x76]	24478	1		T4	242		T9	229		T12	486
valid_sources[0x77]	24986	1		T4	247		T9	213		T12	526
valid_sources[0x78]	24076	1		T4	212		T9	441		T11	1
valid_sources[0x79]	24603	1		T4	231		T9	248		T12	533
valid_sources[0x7a]	23453	1		T4	213		T9	173		T12	501
valid_sources[0x7b]	25059	1		T4	225		T9	47		T12	466
valid_sources[0x7c]	24590	1		T3	4		T4	239		T9	192
valid_sources[0x7d]	23843	1		T4	218		T9	177		T12	597
valid_sources[0x7e]	22735	1		T4	239		T9	33		T12	529
valid_sources[0x7f]	23307	1		T4	256		T9	221		T12	545
valid_sources[0x80]	24734	1		T4	209		T9	204		T11	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1451353

1

T2

22

T4

13679

T5

1

values[0x0]

all_enables

biggest_size

2184225

1

T1

7

T2

115

T3

9

values[0x1]

all_enables

biggest_size

2179886

1

T1

6

T2

105

T3

4