Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	792750082	6876934	0	0
wdog_bark_thold_rd_A	792750082	142276	0	0
wdog_bite_thold_rd_A	792750082	124232	0	0
wdog_ctrl_rd_A	792750082	123708	0	0
wdog_regwen_rd_A	792750082	140558	0	0
wkup_ctrl_rd_A	792750082	124157	0	0
wkup_thold_hi_rd_A	792750082	141461	0	0
wkup_thold_lo_rd_A	792750082	123092	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792750082	6876934	0	0
T4	272866	63271	0	0
T5	448532	0	0	0
T6	158987	0	0	0
T7	44599	0	0	0
T8	27180	0	0	0
T9	297038	98964	0	0
T10	6740	0	0	0
T11	216053	0	0	0
T12	651752	148565	0	0
T13	0	270805	0	0
T14	392304	0	0	0
T22	0	127958	0	0
T23	0	32766	0	0
T32	0	207328	0	0
T33	0	92025	0	0
T34	0	104098	0	0
T35	0	300156	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792750082	142276	0	0
T4	272866	6181	0	0
T5	448532	0	0	0
T6	158987	0	0	0
T7	44599	0	0	0
T8	27180	0	0	0
T9	297038	0	0	0
T10	6740	0	0	0
T11	216053	0	0	0
T12	651752	14147	0	0
T14	392304	0	0	0
T23	0	1602	0	0
T34	0	10616	0	0
T36	0	18729	0	0
T46	0	7833	0	0
T82	0	1442	0	0
T83	0	10408	0	0
T84	0	22560	0	0
T85	0	14814	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792750082	124232	0	0
T4	272866	5581	0	0
T5	448532	0	0	0
T6	158987	0	0	0
T7	44599	0	0	0
T8	27180	0	0	0
T9	297038	0	0	0
T10	6740	0	0	0
T11	216053	0	0	0
T12	651752	12219	0	0
T14	392304	0	0	0
T23	0	1469	0	0
T34	0	9452	0	0
T36	0	16382	0	0
T46	0	6823	0	0
T82	0	1286	0	0
T83	0	9047	0	0
T84	0	19137	0	0
T85	0	13054	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792750082	123708	0	0
T4	272866	4995	0	0
T5	448532	0	0	0
T6	158987	0	0	0
T7	44599	0	0	0
T8	27180	0	0	0
T9	297038	0	0	0
T10	6740	0	0	0
T11	216053	0	0	0
T12	651752	12120	0	0
T14	392304	0	0	0
T23	0	1484	0	0
T34	0	9377	0	0
T36	0	16520	0	0
T46	0	6802	0	0
T82	0	1262	0	0
T83	0	9120	0	0
T84	0	19135	0	0
T85	0	12984	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792750082	140558	0	0
T4	272866	6025	0	0
T5	448532	0	0	0
T6	158987	0	0	0
T7	44599	0	0	0
T8	27180	0	0	0
T9	297038	0	0	0
T10	6740	0	0	0
T11	216053	0	0	0
T12	651752	14025	0	0
T14	392304	0	0	0
T23	0	1597	0	0
T34	0	11054	0	0
T36	0	18612	0	0
T46	0	7237	0	0
T82	0	1364	0	0
T83	0	10084	0	0
T84	0	22510	0	0
T85	0	14358	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792750082	124157	0	0
T4	272866	5083	0	0
T5	448532	0	0	0
T6	158987	0	0	0
T7	44599	0	0	0
T8	27180	0	0	0
T9	297038	0	0	0
T10	6740	0	0	0
T11	216053	0	0	0
T12	651752	12460	0	0
T14	392304	0	0	0
T23	0	1502	0	0
T34	0	9264	0	0
T36	0	16892	0	0
T46	0	6521	0	0
T82	0	1185	0	0
T83	0	8999	0	0
T84	0	19059	0	0
T85	0	12820	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792750082	141461	0	0
T4	272866	5851	0	0
T5	448532	0	0	0
T6	158987	0	0	0
T7	44599	0	0	0
T8	27180	0	0	0
T9	297038	0	0	0
T10	6740	0	0	0
T11	216053	0	0	0
T12	651752	14130	0	0
T14	392304	0	0	0
T23	0	1654	0	0
T34	0	11134	0	0
T36	0	19130	0	0
T46	0	7675	0	0
T82	0	1411	0	0
T83	0	10295	0	0
T84	0	22143	0	0
T85	0	14449	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	792750082	123092	0	0
T4	272866	5346	0	0
T5	448532	0	0	0
T6	158987	0	0	0
T7	44599	0	0	0
T8	27180	0	0	0
T9	297038	0	0	0
T10	6740	0	0	0
T11	216053	0	0	0
T12	651752	12553	0	0
T14	392304	0	0	0
T23	0	1513	0	0
T34	0	9028	0	0
T36	0	15905	0	0
T46	0	6722	0	0
T82	0	1293	0	0
T83	0	8756	0	0
T84	0	19134	0	0
T85	0	13126	0	0