Unified Coverage Report :: Module

Module : aon_timer_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_core	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : aon_timer_core

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
ALWAYS	46	4	4	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	84	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	1	1
42	1	1
46	1	1
47	1	1
48	1	1
49	1	1
			MISSING_ELSE
53	1	1
54	1	1
57	1	1
61	1	1
62	1	1
65	1	1
72	1	1
76	1	1
77	1	1
80	1	1
82	1	1
84	1	1

Cond Coverage for Module : aon_timer_core

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       41
 EXPRESSION (wkup_incr ? 12'b0 : ((prescale_count_q + 12'b1)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       65
 EXPRESSION (wkup_incr & (wkup_count >= wkup_thold))
             ----1----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       80
 EXPRESSION (wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bark_thold.q))
             ----1----   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bite_thold.q))
             ----1----   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Module : aon_timer_core

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	41	2	2	100.00
IF	46	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	41	(wkup_incr) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	46	if ((!rst_aon_ni))
-2-:	48	if (prescale_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3