Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	392133	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4876173	1		T1	13		T2	228		T3	169

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1295453	1		T1	1		T2	63		T3	40
values[0x0]	1863086	1		T1	8		T2	133		T3	115
values[0x1]	2109767	1		T1	10		T2	161		T3	109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	174744	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5093562	1		T1	13		T2	248		T3	188

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21034	1		T2	2		T8	1		T10	4
valid_sources[0x01]	21455	1		T1	1		T2	5		T10	1
valid_sources[0x02]	21868	1		T2	1		T10	1		T16	444
valid_sources[0x03]	21313	1		T10	5		T16	509		T19	121
valid_sources[0x04]	20575	1		T2	1		T10	1		T16	406
valid_sources[0x05]	19993	1		T2	1		T16	465		T19	158
valid_sources[0x06]	20245	1		T2	1		T8	1		T16	497
valid_sources[0x07]	20410	1		T16	463		T19	76		T20	426
valid_sources[0x08]	20687	1		T2	1		T10	2		T13	1
valid_sources[0x09]	21557	1		T2	1		T10	3		T16	511
valid_sources[0x0a]	20509	1		T2	1		T9	1		T16	489
valid_sources[0x0b]	20784	1		T2	1		T16	475		T19	115
valid_sources[0x0c]	21220	1		T2	3		T10	2		T16	486
valid_sources[0x0d]	21231	1		T2	4		T10	1		T16	464
valid_sources[0x0e]	20229	1		T10	5		T11	1		T16	476
valid_sources[0x0f]	20470	1		T2	2		T10	4		T16	484
valid_sources[0x10]	20437	1		T2	2		T10	2		T16	474
valid_sources[0x11]	21617	1		T2	1		T14	2		T16	443
valid_sources[0x12]	20452	1		T2	2		T7	2		T10	1
valid_sources[0x13]	20309	1		T2	3		T16	470		T19	145
valid_sources[0x14]	20472	1		T16	526		T19	137		T52	9
valid_sources[0x15]	20756	1		T2	3		T16	495		T19	124
valid_sources[0x16]	20817	1		T2	4		T10	2		T16	464
valid_sources[0x17]	20779	1		T2	1		T9	2		T15	344
valid_sources[0x18]	19385	1		T2	1		T11	1		T16	454
valid_sources[0x19]	20485	1		T2	1		T10	1		T16	450
valid_sources[0x1a]	20314	1		T2	2		T16	518		T19	166
valid_sources[0x1b]	21216	1		T2	1		T10	3		T16	497
valid_sources[0x1c]	20584	1		T16	463		T19	135		T20	20
valid_sources[0x1d]	19939	1		T2	2		T9	1		T16	463
valid_sources[0x1e]	21244	1		T2	2		T16	460		T19	102
valid_sources[0x1f]	20622	1		T2	2		T8	1		T10	5
valid_sources[0x20]	20171	1		T1	1		T2	2		T10	6
valid_sources[0x21]	20524	1		T1	1		T2	1		T11	1
valid_sources[0x22]	21152	1		T2	3		T16	489		T19	120
valid_sources[0x23]	20642	1		T13	2		T16	457		T19	116
valid_sources[0x24]	21787	1		T10	6		T16	439		T19	132
valid_sources[0x25]	19929	1		T6	1		T7	1		T9	1
valid_sources[0x26]	21041	1		T2	1		T16	470		T19	170
valid_sources[0x27]	19744	1		T2	3		T16	497		T19	120
valid_sources[0x28]	21173	1		T2	5		T16	519		T19	125
valid_sources[0x29]	20859	1		T2	1		T16	482		T19	135
valid_sources[0x2a]	21139	1		T2	4		T10	1		T11	1
valid_sources[0x2b]	20232	1		T2	1		T16	517		T19	198
valid_sources[0x2c]	20390	1		T2	1		T16	425		T19	159
valid_sources[0x2d]	19875	1		T16	524		T19	151		T52	2
valid_sources[0x2e]	20534	1		T2	1		T11	1		T12	1
valid_sources[0x2f]	20767	1		T2	1		T9	2		T16	503
valid_sources[0x30]	19484	1		T16	490		T19	148		T20	35
valid_sources[0x31]	20503	1		T11	1		T16	446		T19	129
valid_sources[0x32]	20159	1		T2	3		T16	452		T19	167
valid_sources[0x33]	21024	1		T2	2		T16	438		T19	91
valid_sources[0x34]	21692	1		T16	434		T19	58		T20	197
valid_sources[0x35]	19826	1		T2	3		T16	471		T19	109
valid_sources[0x36]	20947	1		T2	1		T10	1		T16	457
valid_sources[0x37]	20478	1		T2	4		T10	2		T11	1
valid_sources[0x38]	21396	1		T1	1		T16	507		T19	158
valid_sources[0x39]	20308	1		T10	3		T18	2		T13	1
valid_sources[0x3a]	19930	1		T2	4		T10	3		T16	446
valid_sources[0x3b]	20059	1		T2	1		T10	2		T13	1
valid_sources[0x3c]	20446	1		T9	2		T10	1		T16	453
valid_sources[0x3d]	20815	1		T16	446		T19	199		T20	241
valid_sources[0x3e]	20271	1		T2	1		T10	5		T16	497
valid_sources[0x3f]	21987	1		T10	1		T16	476		T19	93
valid_sources[0x40]	21351	1		T1	1		T2	1		T6	1
valid_sources[0x41]	21130	1		T2	2		T7	2		T10	5
valid_sources[0x42]	20068	1		T1	1		T16	469		T19	148
valid_sources[0x43]	20993	1		T2	2		T8	2		T10	4
valid_sources[0x44]	20062	1		T10	1		T13	2		T14	3
valid_sources[0x45]	20762	1		T10	2		T16	473		T19	138
valid_sources[0x46]	20337	1		T1	1		T2	1		T16	456
valid_sources[0x47]	20582	1		T2	2		T13	2		T16	455
valid_sources[0x48]	21270	1		T2	2		T10	1		T16	470
valid_sources[0x49]	20566	1		T2	3		T16	455		T19	98
valid_sources[0x4a]	22034	1		T2	1		T10	3		T16	439
valid_sources[0x4b]	20938	1		T2	2		T16	495		T19	166
valid_sources[0x4c]	20142	1		T10	2		T16	465		T19	108
valid_sources[0x4d]	19255	1		T7	1		T16	468		T19	143
valid_sources[0x4e]	20884	1		T2	3		T8	1		T11	1
valid_sources[0x4f]	20526	1		T1	1		T2	3		T16	432
valid_sources[0x50]	20536	1		T2	1		T12	1		T16	485
valid_sources[0x51]	20698	1		T2	1		T16	511		T19	167
valid_sources[0x52]	21041	1		T2	3		T18	5		T16	451
valid_sources[0x53]	20729	1		T12	1		T16	436		T19	119
valid_sources[0x54]	20152	1		T9	1		T11	2		T16	455
valid_sources[0x55]	20443	1		T16	537		T19	189		T52	2
valid_sources[0x56]	20067	1		T2	2		T16	438		T19	199
valid_sources[0x57]	20376	1		T2	1		T16	555		T19	191
valid_sources[0x58]	21590	1		T2	1		T10	4		T18	1
valid_sources[0x59]	20696	1		T16	551		T19	111		T20	641
valid_sources[0x5a]	20538	1		T2	3		T16	467		T19	176
valid_sources[0x5b]	20804	1		T2	1		T6	1		T10	1
valid_sources[0x5c]	20685	1		T10	1		T16	470		T19	177
valid_sources[0x5d]	20325	1		T16	454		T19	192		T20	166
valid_sources[0x5e]	20729	1		T2	3		T7	1		T10	1
valid_sources[0x5f]	21582	1		T2	1		T10	3		T16	448
valid_sources[0x60]	19717	1		T10	3		T16	473		T19	130
valid_sources[0x61]	20184	1		T10	2		T11	1		T16	492
valid_sources[0x62]	21651	1		T10	2		T16	486		T51	1
valid_sources[0x63]	20262	1		T1	1		T2	1		T16	466
valid_sources[0x64]	20613	1		T2	2		T16	490		T19	169
valid_sources[0x65]	20810	1		T2	1		T16	506		T19	136
valid_sources[0x66]	20798	1		T2	3		T10	3		T11	1
valid_sources[0x67]	21049	1		T1	2		T2	2		T6	2
valid_sources[0x68]	20075	1		T2	2		T7	1		T16	516
valid_sources[0x69]	20057	1		T2	1		T10	1		T16	489
valid_sources[0x6a]	21735	1		T16	460		T19	133		T20	45
valid_sources[0x6b]	21626	1		T2	2		T10	2		T16	473
valid_sources[0x6c]	20923	1		T2	2		T10	8		T13	1
valid_sources[0x6d]	20189	1		T2	1		T10	1		T16	433
valid_sources[0x6e]	21718	1		T2	1		T16	488		T19	141
valid_sources[0x6f]	20484	1		T2	3		T8	1		T11	1
valid_sources[0x70]	20516	1		T2	1		T7	1		T16	488
valid_sources[0x71]	20452	1		T2	2		T10	3		T16	471
valid_sources[0x72]	20091	1		T7	1		T16	485		T19	108
valid_sources[0x73]	21462	1		T2	1		T8	1		T10	4
valid_sources[0x74]	20678	1		T10	2		T16	523		T19	147
valid_sources[0x75]	20222	1		T2	1		T10	4		T16	459
valid_sources[0x76]	20487	1		T2	4		T9	1		T16	477
valid_sources[0x77]	20460	1		T2	2		T8	1		T14	1
valid_sources[0x78]	18899	1		T2	2		T10	3		T16	469
valid_sources[0x79]	19769	1		T2	3		T9	1		T16	422
valid_sources[0x7a]	21251	1		T9	1		T10	2		T12	3
valid_sources[0x7b]	20262	1		T7	1		T16	459		T19	112
valid_sources[0x7c]	21344	1		T10	6		T16	508		T19	213
valid_sources[0x7d]	19572	1		T2	4		T16	505		T19	77
valid_sources[0x7e]	21170	1		T2	1		T16	469		T19	180
valid_sources[0x7f]	20358	1		T2	3		T16	445		T19	175
valid_sources[0x80]	20058	1		T2	1		T16	514		T19	57

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1215861

1

T1

1

T2

32

T3

20

values[0x0]

all_enables

biggest_size

1830746

1

T1

4

T2

90

T3

79

values[0x1]

all_enables

biggest_size

1829566

1

T1

8

T2

106

T3

70