Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	386737	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4805942	1		T1	259		T2	14		T3	20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1276638	1		T1	38		T2	1		T3	1
values[0x0]	1835657	1		T1	155		T2	8		T3	13
values[0x1]	2080384	1		T1	173		T2	11		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	172065	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5020614	1		T1	275		T2	14		T3	20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19786	1		T3	1		T13	660		T15	91
valid_sources[0x01]	20999	1		T3	1		T13	681		T15	105
valid_sources[0x02]	19478	1		T13	638		T15	129		T16	641
valid_sources[0x03]	20309	1		T13	633		T15	91		T16	569
valid_sources[0x04]	21746	1		T13	644		T15	102		T16	616
valid_sources[0x05]	21498	1		T13	625		T15	102		T16	597
valid_sources[0x06]	18630	1		T3	1		T13	595		T15	92
valid_sources[0x07]	19744	1		T8	1		T13	579		T15	78
valid_sources[0x08]	20564	1		T13	647		T15	80		T16	606
valid_sources[0x09]	20656	1		T5	1		T13	664		T15	93
valid_sources[0x0a]	20274	1		T8	1		T13	588		T15	105
valid_sources[0x0b]	20495	1		T8	3		T13	615		T15	93
valid_sources[0x0c]	18519	1		T13	643		T15	76		T16	592
valid_sources[0x0d]	20018	1		T3	1		T13	623		T15	107
valid_sources[0x0e]	18885	1		T10	16		T13	649		T15	82
valid_sources[0x0f]	19925	1		T5	1		T13	691		T15	111
valid_sources[0x10]	19323	1		T5	1		T13	607		T15	86
valid_sources[0x11]	20377	1		T13	607		T15	109		T16	571
valid_sources[0x12]	20025	1		T13	657		T15	78		T16	600
valid_sources[0x13]	21951	1		T10	13		T13	541		T15	99
valid_sources[0x14]	21005	1		T13	674		T15	106		T16	614
valid_sources[0x15]	18623	1		T3	1		T13	665		T15	107
valid_sources[0x16]	20353	1		T10	4		T13	651		T15	90
valid_sources[0x17]	19653	1		T13	646		T15	86		T16	641
valid_sources[0x18]	21452	1		T13	557		T15	99		T16	611
valid_sources[0x19]	20091	1		T13	690		T15	102		T16	637
valid_sources[0x1a]	20426	1		T13	603		T15	94		T16	554
valid_sources[0x1b]	19995	1		T13	663		T15	99		T16	596
valid_sources[0x1c]	19707	1		T13	618		T15	109		T16	578
valid_sources[0x1d]	18790	1		T4	5		T5	2		T10	6
valid_sources[0x1e]	20751	1		T13	635		T15	122		T16	609
valid_sources[0x1f]	19687	1		T13	597		T15	102		T16	601
valid_sources[0x20]	19222	1		T13	630		T15	102		T16	600
valid_sources[0x21]	20627	1		T13	640		T15	107		T16	625
valid_sources[0x22]	20988	1		T3	1		T13	659		T24	1
valid_sources[0x23]	19165	1		T3	1		T13	558		T15	99
valid_sources[0x24]	19250	1		T9	1		T13	615		T15	98
valid_sources[0x25]	19213	1		T8	1		T13	626		T24	1
valid_sources[0x26]	18887	1		T9	2		T13	603		T15	92
valid_sources[0x27]	21159	1		T5	1		T13	557		T15	113
valid_sources[0x28]	20426	1		T13	642		T15	89		T16	602
valid_sources[0x29]	19089	1		T8	1		T13	638		T24	2
valid_sources[0x2a]	20381	1		T13	647		T15	89		T16	620
valid_sources[0x2b]	20464	1		T13	552		T15	98		T16	621
valid_sources[0x2c]	20687	1		T5	1		T10	9		T13	632
valid_sources[0x2d]	21289	1		T13	688		T15	80		T16	599
valid_sources[0x2e]	19315	1		T13	604		T15	101		T16	649
valid_sources[0x2f]	18856	1		T13	604		T15	93		T16	628
valid_sources[0x30]	21028	1		T8	1		T13	647		T15	86
valid_sources[0x31]	20693	1		T5	1		T13	646		T15	71
valid_sources[0x32]	21434	1		T8	1		T13	628		T15	94
valid_sources[0x33]	19562	1		T13	674		T15	86		T16	590
valid_sources[0x34]	20360	1		T8	1		T13	670		T15	73
valid_sources[0x35]	21106	1		T13	590		T15	106		T16	597
valid_sources[0x36]	18826	1		T13	682		T24	2		T15	96
valid_sources[0x37]	19602	1		T13	650		T15	117		T16	579
valid_sources[0x38]	21435	1		T13	605		T15	99		T16	584
valid_sources[0x39]	19359	1		T13	649		T15	91		T16	601
valid_sources[0x3a]	19884	1		T13	720		T15	82		T16	623
valid_sources[0x3b]	20436	1		T12	20		T13	608		T15	95
valid_sources[0x3c]	22345	1		T13	614		T15	110		T16	602
valid_sources[0x3d]	20944	1		T13	589		T15	86		T16	598
valid_sources[0x3e]	20442	1		T3	1		T13	603		T15	111
valid_sources[0x3f]	20232	1		T13	657		T15	107		T16	616
valid_sources[0x40]	20072	1		T13	638		T15	100		T16	589
valid_sources[0x41]	19988	1		T3	1		T5	1		T10	4
valid_sources[0x42]	20917	1		T13	626		T15	103		T16	569
valid_sources[0x43]	21152	1		T2	3		T13	601		T15	84
valid_sources[0x44]	21553	1		T8	1		T13	637		T15	85
valid_sources[0x45]	20290	1		T13	665		T15	93		T16	591
valid_sources[0x46]	20767	1		T13	623		T15	82		T16	592
valid_sources[0x47]	20275	1		T13	660		T15	109		T16	614
valid_sources[0x48]	20914	1		T13	540		T15	87		T16	604
valid_sources[0x49]	20596	1		T5	1		T10	2		T13	615
valid_sources[0x4a]	18464	1		T10	7		T13	570		T15	98
valid_sources[0x4b]	20053	1		T13	616		T15	98		T16	577
valid_sources[0x4c]	21647	1		T9	1		T13	638		T15	89
valid_sources[0x4d]	20852	1		T13	606		T15	100		T16	589
valid_sources[0x4e]	20292	1		T13	636		T15	116		T16	604
valid_sources[0x4f]	20384	1		T13	640		T15	106		T16	629
valid_sources[0x50]	19969	1		T13	630		T15	74		T16	647
valid_sources[0x51]	20434	1		T9	1		T13	649		T15	91
valid_sources[0x52]	21466	1		T5	2		T13	564		T15	112
valid_sources[0x53]	20672	1		T13	648		T15	108		T16	673
valid_sources[0x54]	18881	1		T3	1		T13	614		T15	101
valid_sources[0x55]	20333	1		T3	2		T13	619		T15	112
valid_sources[0x56]	20127	1		T13	595		T15	92		T16	647
valid_sources[0x57]	20131	1		T5	1		T13	597		T15	103
valid_sources[0x58]	21726	1		T13	626		T15	106		T16	604
valid_sources[0x59]	18391	1		T13	644		T15	104		T16	575
valid_sources[0x5a]	19057	1		T10	13		T13	674		T15	89
valid_sources[0x5b]	20287	1		T5	1		T7	19		T13	605
valid_sources[0x5c]	21863	1		T5	1		T13	659		T15	90
valid_sources[0x5d]	20640	1		T13	627		T15	101		T16	638
valid_sources[0x5e]	19704	1		T3	1		T13	609		T15	95
valid_sources[0x5f]	20134	1		T13	635		T15	104		T16	581
valid_sources[0x60]	21335	1		T13	623		T15	93		T16	644
valid_sources[0x61]	20745	1		T13	651		T15	90		T16	641
valid_sources[0x62]	20307	1		T8	1		T13	609		T15	108
valid_sources[0x63]	20443	1		T13	647		T15	94		T16	639
valid_sources[0x64]	19385	1		T4	1		T13	619		T15	83
valid_sources[0x65]	21662	1		T13	612		T15	103		T16	547
valid_sources[0x66]	19243	1		T13	628		T24	2		T15	83
valid_sources[0x67]	19676	1		T13	690		T15	103		T16	617
valid_sources[0x68]	22227	1		T8	1		T13	598		T15	113
valid_sources[0x69]	19066	1		T13	698		T15	100		T16	598
valid_sources[0x6a]	19224	1		T13	680		T15	86		T16	604
valid_sources[0x6b]	19760	1		T3	1		T9	4		T13	661
valid_sources[0x6c]	21566	1		T13	551		T15	101		T16	582
valid_sources[0x6d]	19619	1		T3	1		T13	614		T15	100
valid_sources[0x6e]	19736	1		T13	619		T15	103		T16	618
valid_sources[0x6f]	21637	1		T13	728		T15	122		T16	610
valid_sources[0x70]	20681	1		T13	663		T15	95		T16	590
valid_sources[0x71]	20632	1		T9	5		T13	631		T15	109
valid_sources[0x72]	19427	1		T13	635		T15	82		T16	613
valid_sources[0x73]	21381	1		T13	665		T15	105		T16	580
valid_sources[0x74]	20834	1		T10	2		T13	625		T15	110
valid_sources[0x75]	20905	1		T13	642		T15	103		T16	644
valid_sources[0x76]	19548	1		T13	675		T15	93		T16	618
valid_sources[0x77]	19885	1		T13	643		T15	89		T16	598
valid_sources[0x78]	19727	1		T13	649		T15	119		T16	594
valid_sources[0x79]	21077	1		T13	596		T15	86		T16	603
valid_sources[0x7a]	20921	1		T13	600		T15	107		T16	583
valid_sources[0x7b]	19923	1		T13	621		T15	103		T16	598
valid_sources[0x7c]	20386	1		T13	610		T15	82		T16	634
valid_sources[0x7d]	19575	1		T10	29		T13	638		T15	87
valid_sources[0x7e]	20915	1		T13	642		T15	113		T16	632
valid_sources[0x7f]	19362	1		T10	10		T13	671		T15	82
valid_sources[0x80]	19834	1		T8	1		T13	666		T15	91

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1198768

1

T1

17

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1803150

1

T1

112

T2

7

T3

12

values[0x1]

all_enables

biggest_size

1804024

1

T1

130

T2

6

T3

7