Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	667195541	5636364	0	0
wdog_bark_thold_rd_A	667195541	201441	0	0
wdog_bite_thold_rd_A	667195541	176068	0	0
wdog_ctrl_rd_A	667195541	176709	0	0
wdog_regwen_rd_A	667195541	200723	0	0
wkup_ctrl_rd_A	667195541	177750	0	0
wkup_thold_hi_rd_A	667195541	200927	0	0
wkup_thold_lo_rd_A	667195541	177246	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667195541	5636364	0	0
T13	747055	164899	0	0
T14	377676	0	0	0
T15	105758	26450	0	0
T16	661695	178173	0	0
T20	862053	0	0	0
T24	56367	0	0	0
T25	19775	0	0	0
T26	0	88304	0	0
T27	29928	0	0	0
T33	0	179116	0	0
T34	0	116293	0	0
T35	0	157345	0	0
T36	0	29297	0	0
T37	0	124179	0	0
T38	0	75466	0	0
T39	912525	0	0	0
T40	42896	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667195541	201441	0	0
T13	747055	17101	0	0
T14	377676	0	0	0
T15	105758	1274	0	0
T16	661695	0	0	0
T20	862053	0	0	0
T24	56367	0	0	0
T25	19775	0	0	0
T27	29928	0	0	0
T34	0	11372	0	0
T35	0	15849	0	0
T37	0	11392	0	0
T39	912525	0	0	0
T40	42896	0	0	0
T75	0	6415	0	0
T76	0	32016	0	0
T77	0	3255	0	0
T78	0	3132	0	0
T79	0	16815	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667195541	176068	0	0
T13	747055	15709	0	0
T14	377676	0	0	0
T15	105758	1261	0	0
T16	661695	0	0	0
T20	862053	0	0	0
T24	56367	0	0	0
T25	19775	0	0	0
T27	29928	0	0	0
T34	0	10077	0	0
T35	0	14271	0	0
T37	0	10019	0	0
T39	912525	0	0	0
T40	42896	0	0	0
T75	0	5478	0	0
T76	0	27656	0	0
T77	0	3021	0	0
T78	0	2820	0	0
T79	0	14649	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667195541	176709	0	0
T13	747055	15565	0	0
T14	377676	0	0	0
T15	105758	1361	0	0
T16	661695	0	0	0
T20	862053	0	0	0
T24	56367	0	0	0
T25	19775	0	0	0
T27	29928	0	0	0
T34	0	9926	0	0
T35	0	14025	0	0
T37	0	10115	0	0
T39	912525	0	0	0
T40	42896	0	0	0
T75	0	5806	0	0
T76	0	28051	0	0
T77	0	3029	0	0
T78	0	2715	0	0
T79	0	15193	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667195541	200723	0	0
T13	747055	17966	0	0
T14	377676	0	0	0
T15	105758	1326	0	0
T16	661695	0	0	0
T20	862053	0	0	0
T24	56367	0	0	0
T25	19775	0	0	0
T27	29928	0	0	0
T34	0	11648	0	0
T35	0	16365	0	0
T37	0	11433	0	0
T39	912525	0	0	0
T40	42896	0	0	0
T75	0	6383	0	0
T76	0	31295	0	0
T77	0	3657	0	0
T78	0	3132	0	0
T79	0	16147	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667195541	177750	0	0
T13	747055	15186	0	0
T14	377676	0	0	0
T15	105758	1279	0	0
T16	661695	0	0	0
T20	862053	0	0	0
T24	56367	0	0	0
T25	19775	0	0	0
T27	29928	0	0	0
T34	0	9811	0	0
T35	0	14497	0	0
T37	0	10677	0	0
T39	912525	0	0	0
T40	42896	0	0	0
T75	0	5759	0	0
T76	0	28308	0	0
T77	0	3126	0	0
T78	0	2508	0	0
T79	0	15064	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667195541	200927	0	0
T13	747055	17534	0	0
T14	377676	0	0	0
T15	105758	1379	0	0
T16	661695	0	0	0
T20	862053	0	0	0
T24	56367	0	0	0
T25	19775	0	0	0
T27	29928	0	0	0
T34	0	11499	0	0
T35	0	15704	0	0
T37	0	11985	0	0
T39	912525	0	0	0
T40	42896	0	0	0
T75	0	6653	0	0
T76	0	32016	0	0
T77	0	3500	0	0
T78	0	3127	0	0
T79	0	16340	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667195541	177246	0	0
T13	747055	15468	0	0
T14	377676	0	0	0
T15	105758	1203	0	0
T16	661695	0	0	0
T20	862053	0	0	0
T24	56367	0	0	0
T25	19775	0	0	0
T27	29928	0	0	0
T34	0	9999	0	0
T35	0	14119	0	0
T37	0	10377	0	0
T39	912525	0	0	0
T40	42896	0	0	0
T75	0	5618	0	0
T76	0	27997	0	0
T77	0	3181	0	0
T78	0	2596	0	0
T79	0	15068	0	0