Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	389032	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4780522	1		T1	14		T2	17		T3	249673

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1269903	1		T1	1		T2	1		T3	66318
values[0x0]	1829782	1		T1	6		T2	11		T3	95016
values[0x1]	2069869	1		T1	13		T2	10		T3	107575

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	172706	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4996848	1		T1	16		T2	18		T3	260752

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18765	1		T3	1052		T5	2		T6	1102
valid_sources[0x01]	20984	1		T2	1		T3	1011		T5	1
valid_sources[0x02]	21883	1		T3	996		T6	1053		T7	514
valid_sources[0x03]	19181	1		T3	1011		T6	1110		T7	478
valid_sources[0x04]	21177	1		T3	1018		T5	3		T6	1066
valid_sources[0x05]	21107	1		T3	1084		T5	3		T6	1095
valid_sources[0x06]	21054	1		T3	1046		T5	1		T6	1054
valid_sources[0x07]	19525	1		T3	1049		T5	1		T6	1119
valid_sources[0x08]	22441	1		T3	1041		T6	1105		T7	483
valid_sources[0x09]	20533	1		T3	1113		T6	1083		T7	509
valid_sources[0x0a]	19057	1		T3	1083		T6	1076		T7	516
valid_sources[0x0b]	21414	1		T3	1040		T5	2		T6	1072
valid_sources[0x0c]	18790	1		T3	1046		T5	1		T6	1099
valid_sources[0x0d]	19882	1		T2	1		T3	1055		T5	2
valid_sources[0x0e]	18388	1		T3	1069		T6	1091		T7	497
valid_sources[0x0f]	21117	1		T3	985		T5	1		T6	1128
valid_sources[0x10]	20335	1		T3	1006		T6	1099		T7	493
valid_sources[0x11]	19142	1		T1	2		T3	1076		T5	2
valid_sources[0x12]	21023	1		T3	1068		T5	1		T6	1052
valid_sources[0x13]	21404	1		T3	1093		T5	1		T6	1032
valid_sources[0x14]	21724	1		T1	1		T3	1076		T5	2
valid_sources[0x15]	19523	1		T2	1		T3	1056		T5	3
valid_sources[0x16]	18310	1		T3	1058		T6	1075		T7	531
valid_sources[0x17]	18875	1		T3	1044		T5	3		T6	1128
valid_sources[0x18]	21723	1		T3	1020		T5	4		T6	1102
valid_sources[0x19]	19101	1		T1	1		T3	1111		T6	1028
valid_sources[0x1a]	21113	1		T3	1051		T6	1114		T7	448
valid_sources[0x1b]	20221	1		T3	1055		T5	2		T6	1052
valid_sources[0x1c]	20884	1		T3	1039		T5	1		T6	1093
valid_sources[0x1d]	20656	1		T3	1041		T5	4		T6	1061
valid_sources[0x1e]	19567	1		T3	930		T6	1088		T7	510
valid_sources[0x1f]	20487	1		T3	1067		T5	4		T6	1083
valid_sources[0x20]	19227	1		T3	1057		T6	1013		T7	498
valid_sources[0x21]	22495	1		T3	1049		T5	3		T6	1072
valid_sources[0x22]	21030	1		T3	1091		T5	3		T6	1088
valid_sources[0x23]	19888	1		T3	1105		T6	1079		T7	489
valid_sources[0x24]	21615	1		T3	1054		T5	4		T6	1110
valid_sources[0x25]	20028	1		T3	1084		T6	1092		T7	494
valid_sources[0x26]	18263	1		T3	1004		T5	2		T6	1130
valid_sources[0x27]	18662	1		T3	1042		T5	5		T6	1025
valid_sources[0x28]	20356	1		T1	1		T3	1085		T5	1
valid_sources[0x29]	20700	1		T3	1032		T6	1063		T7	495
valid_sources[0x2a]	19966	1		T3	1015		T5	2		T6	1108
valid_sources[0x2b]	19468	1		T3	1086		T5	6		T6	1083
valid_sources[0x2c]	21581	1		T3	1039		T6	1082		T7	484
valid_sources[0x2d]	20678	1		T3	1056		T5	1		T6	1016
valid_sources[0x2e]	19318	1		T3	1102		T6	1038		T7	518
valid_sources[0x2f]	19987	1		T3	1067		T5	3		T6	1122
valid_sources[0x30]	21172	1		T3	1015		T6	1107		T7	480
valid_sources[0x31]	21077	1		T3	1063		T5	2		T6	1115
valid_sources[0x32]	20550	1		T3	1054		T5	1		T6	1105
valid_sources[0x33]	20643	1		T3	1105		T5	1		T6	1123
valid_sources[0x34]	20254	1		T3	1048		T5	1		T6	1052
valid_sources[0x35]	20761	1		T3	1026		T6	1057		T7	473
valid_sources[0x36]	19172	1		T3	1049		T5	2		T6	1124
valid_sources[0x37]	20366	1		T3	1083		T5	4		T6	1105
valid_sources[0x38]	21253	1		T3	987		T6	1068		T7	505
valid_sources[0x39]	20698	1		T3	1076		T5	2		T6	1138
valid_sources[0x3a]	21034	1		T3	1009		T5	2		T6	1077
valid_sources[0x3b]	19998	1		T3	1060		T5	2		T6	1109
valid_sources[0x3c]	20397	1		T3	1041		T5	2		T6	1092
valid_sources[0x3d]	20909	1		T3	1045		T5	2		T6	1123
valid_sources[0x3e]	20172	1		T3	1040		T6	1090		T7	537
valid_sources[0x3f]	17803	1		T3	1078		T5	3		T6	1098
valid_sources[0x40]	20415	1		T3	1005		T5	1		T6	1052
valid_sources[0x41]	20406	1		T3	1087		T6	1068		T7	489
valid_sources[0x42]	20046	1		T2	1		T3	1041		T5	1
valid_sources[0x43]	18618	1		T3	1081		T5	2		T6	1069
valid_sources[0x44]	20005	1		T3	1069		T5	1		T6	1027
valid_sources[0x45]	22117	1		T3	956		T6	1087		T7	523
valid_sources[0x46]	20645	1		T3	1067		T5	2		T6	1109
valid_sources[0x47]	19286	1		T3	1076		T5	9		T6	1156
valid_sources[0x48]	20852	1		T3	1081		T5	3		T6	1095
valid_sources[0x49]	19253	1		T3	1095		T5	3		T6	1147
valid_sources[0x4a]	19059	1		T3	1009		T6	1015		T7	496
valid_sources[0x4b]	20370	1		T3	1019		T6	1149		T7	479
valid_sources[0x4c]	19325	1		T3	1042		T5	2		T6	1034
valid_sources[0x4d]	21336	1		T2	1		T3	1066		T5	1
valid_sources[0x4e]	20806	1		T3	1035		T5	1		T6	1056
valid_sources[0x4f]	20127	1		T3	1055		T5	5		T6	1114
valid_sources[0x50]	17890	1		T3	1047		T5	3		T6	1089
valid_sources[0x51]	20340	1		T3	1076		T5	1		T6	1098
valid_sources[0x52]	19911	1		T3	1026		T5	1		T6	1107
valid_sources[0x53]	19351	1		T3	1031		T5	8		T6	1087
valid_sources[0x54]	19375	1		T3	1042		T5	2		T6	1112
valid_sources[0x55]	22610	1		T2	1		T3	1079		T6	1064
valid_sources[0x56]	20495	1		T3	1043		T5	2		T6	1068
valid_sources[0x57]	20264	1		T2	1		T3	1103		T5	1
valid_sources[0x58]	19153	1		T3	984		T5	1		T6	1114
valid_sources[0x59]	19219	1		T1	1		T3	1033		T6	1019
valid_sources[0x5a]	18991	1		T1	2		T3	1096		T5	1
valid_sources[0x5b]	20217	1		T3	1051		T5	4		T6	1065
valid_sources[0x5c]	20184	1		T3	1097		T5	2		T6	1099
valid_sources[0x5d]	21552	1		T3	1084		T6	986		T7	536
valid_sources[0x5e]	20703	1		T2	1		T3	1041		T6	1072
valid_sources[0x5f]	21257	1		T3	1048		T5	1		T6	1083
valid_sources[0x60]	19540	1		T3	1091		T5	4		T6	1024
valid_sources[0x61]	21764	1		T3	1060		T6	1130		T7	459
valid_sources[0x62]	20789	1		T3	1045		T6	1147		T7	532
valid_sources[0x63]	20617	1		T3	1164		T5	3		T6	1103
valid_sources[0x64]	19496	1		T3	1105		T5	3		T6	1091
valid_sources[0x65]	22855	1		T1	1		T3	1111		T5	1
valid_sources[0x66]	19907	1		T3	994		T5	2		T6	1097
valid_sources[0x67]	21817	1		T3	1029		T5	2		T6	1151
valid_sources[0x68]	19792	1		T3	1062		T5	1		T6	1106
valid_sources[0x69]	19874	1		T3	1068		T5	1		T6	1091
valid_sources[0x6a]	20790	1		T3	1012		T5	2		T6	1063
valid_sources[0x6b]	18831	1		T1	1		T3	1089		T6	1096
valid_sources[0x6c]	18913	1		T2	1		T3	1102		T6	1071
valid_sources[0x6d]	18142	1		T3	999		T6	1120		T7	527
valid_sources[0x6e]	20867	1		T3	974		T5	1		T6	1016
valid_sources[0x6f]	20072	1		T2	1		T3	1020		T5	1
valid_sources[0x70]	20299	1		T3	1032		T5	2		T6	1114
valid_sources[0x71]	20801	1		T3	1047		T6	1088		T7	508
valid_sources[0x72]	20438	1		T3	1023		T5	2		T6	1107
valid_sources[0x73]	20550	1		T3	1049		T5	1		T6	1091
valid_sources[0x74]	21257	1		T3	1110		T5	1		T6	1070
valid_sources[0x75]	21917	1		T3	1056		T6	1135		T7	468
valid_sources[0x76]	21092	1		T3	1037		T5	2		T6	1047
valid_sources[0x77]	17494	1		T3	1106		T5	1		T6	1114
valid_sources[0x78]	21481	1		T2	1		T3	1043		T5	2
valid_sources[0x79]	20161	1		T3	1099		T6	1117		T7	500
valid_sources[0x7a]	20389	1		T3	1033		T5	3		T6	1104
valid_sources[0x7b]	18961	1		T1	3		T3	1047		T5	3
valid_sources[0x7c]	19987	1		T3	1064		T6	1085		T7	507
valid_sources[0x7d]	19115	1		T3	1053		T5	1		T6	1027
valid_sources[0x7e]	20786	1		T3	960		T5	2		T6	1088
valid_sources[0x7f]	19450	1		T3	1078		T6	992		T7	491
valid_sources[0x80]	18476	1		T3	1059		T5	4		T6	1041

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1191380

1

T3

62567

T5

26

T6

63761

values[0x0]

all_enables

biggest_size

1797487

1

T1

5

T2

9

T3

93613

values[0x1]

all_enables

biggest_size

1791655

1

T1

9

T2

8

T3

93493