Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	696867794	5691529	0	0
wdog_bark_thold_rd_A	696867794	109056	0	0
wdog_bite_thold_rd_A	696867794	96911	0	0
wdog_ctrl_rd_A	696867794	95166	0	0
wdog_regwen_rd_A	696867794	109318	0	0
wkup_ctrl_rd_A	696867794	95245	0	0
wkup_thold_hi_rd_A	696867794	108240	0	0
wkup_thold_lo_rd_A	696867794	95806	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696867794	5691529	0	0
T3	106297	294921	0	0
T5	211649	0	0	0
T6	136525	326022	0	0
T7	577258	141198	0	0
T8	190336	0	0	0
T9	7464	0	0	0
T10	10934	0	0	0
T11	254932	58717	0	0
T12	646131	0	0	0
T13	367670	56506	0	0
T28	0	92037	0	0
T29	0	95637	0	0
T30	0	158289	0	0
T31	0	48450	0	0
T32	0	258311	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696867794	109056	0	0
T7	577258	7665	0	0
T8	190336	0	0	0
T9	7464	0	0	0
T10	10934	0	0	0
T11	254932	3232	0	0
T12	646131	0	0	0
T13	367670	0	0	0
T14	13615	0	0	0
T28	380479	0	0	0
T29	0	10037	0	0
T33	372367	0	0	0
T47	0	17464	0	0
T80	0	6566	0	0
T83	0	6748	0	0
T84	0	9625	0	0
T85	0	3101	0	0
T86	0	3642	0	0
T87	0	1029	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696867794	96911	0	0
T7	577258	6782	0	0
T8	190336	0	0	0
T9	7464	0	0	0
T10	10934	0	0	0
T11	254932	2798	0	0
T12	646131	0	0	0
T13	367670	0	0	0
T14	13615	0	0	0
T28	380479	0	0	0
T29	0	8516	0	0
T33	372367	0	0	0
T47	0	15855	0	0
T80	0	5840	0	0
T83	0	5753	0	0
T84	0	8366	0	0
T85	0	2715	0	0
T86	0	3331	0	0
T87	0	1001	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696867794	95166	0	0
T7	577258	6871	0	0
T8	190336	0	0	0
T9	7464	0	0	0
T10	10934	0	0	0
T11	254932	2880	0	0
T12	646131	0	0	0
T13	367670	0	0	0
T14	13615	0	0	0
T28	380479	0	0	0
T29	0	8672	0	0
T33	372367	0	0	0
T47	0	15307	0	0
T80	0	5708	0	0
T83	0	6264	0	0
T84	0	8100	0	0
T85	0	2599	0	0
T86	0	3523	0	0
T87	0	983	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696867794	109318	0	0
T7	577258	7711	0	0
T8	190336	0	0	0
T9	7464	0	0	0
T10	10934	0	0	0
T11	254932	2995	0	0
T12	646131	0	0	0
T13	367670	0	0	0
T14	13615	0	0	0
T28	380479	0	0	0
T29	0	10126	0	0
T33	372367	0	0	0
T47	0	17313	0	0
T80	0	6483	0	0
T83	0	6714	0	0
T84	0	9656	0	0
T85	0	3176	0	0
T86	0	3592	0	0
T87	0	1079	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696867794	95245	0	0
T7	577258	6582	0	0
T8	190336	0	0	0
T9	7464	0	0	0
T10	10934	0	0	0
T11	254932	2669	0	0
T12	646131	0	0	0
T13	367670	0	0	0
T14	13615	0	0	0
T28	380479	0	0	0
T29	0	8660	0	0
T33	372367	0	0	0
T47	0	15958	0	0
T80	0	5438	0	0
T83	0	6203	0	0
T84	0	8056	0	0
T85	0	2514	0	0
T86	0	3227	0	0
T87	0	853	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696867794	108240	0	0
T7	577258	7539	0	0
T8	190336	0	0	0
T9	7464	0	0	0
T10	10934	0	0	0
T11	254932	3092	0	0
T12	646131	0	0	0
T13	367670	0	0	0
T14	13615	0	0	0
T28	380479	0	0	0
T29	0	10036	0	0
T33	372367	0	0	0
T47	0	17917	0	0
T80	0	6632	0	0
T83	0	6360	0	0
T84	0	9314	0	0
T85	0	3021	0	0
T86	0	3901	0	0
T87	0	1005	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696867794	95806	0	0
T7	577258	6994	0	0
T8	190336	0	0	0
T9	7464	0	0	0
T10	10934	0	0	0
T11	254932	2724	0	0
T12	646131	0	0	0
T13	367670	0	0	0
T14	13615	0	0	0
T28	380479	0	0	0
T29	0	8446	0	0
T33	372367	0	0	0
T47	0	15727	0	0
T80	0	5447	0	0
T83	0	6173	0	0
T84	0	7865	0	0
T85	0	2546	0	0
T86	0	3377	0	0
T87	0	951	0	0