Module Definition
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Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
57.42 86.00 69.77 73.91 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.06 92.86 67.35 86.05 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.86 100.00 71.43 100.00 100.00 u_wkup_count_hi_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 93.02 95.65 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 87.76 97.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.21 100.00 92.86 100.00 100.00 u_wkup_count_lo_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 93.02 95.65 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 87.76 97.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.21 100.00 92.86 100.00 100.00 u_wdog_count_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 93.02 95.65 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 87.76 97.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.44 100.00 93.75 100.00 100.00 u_wkup_cause_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_ctrl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_thold_hi_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wkup_thold_lo_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wdog_ctrl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wdog_bark_thold_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wdog_bite_thold_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=13,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=2,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=32,ResetVal=0,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
57.42 86.00
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb

SCORELINE
97.17 100.00
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb

SCORELINE
97.17 100.00
tb.dut.u_reg.u_wdog_count_cdc.u_arb

SCORELINE
97.17 100.00
tb.dut.u_reg.u_wkup_cause_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS1551010100.00
CONT_ASSIGN18311100.00
ALWAYS1871919100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=13,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=2,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=32,ResetVal=0,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
57.42 69.77
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb

SCORECOND
97.17 93.02
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb

SCORECOND
97.17 93.02
tb.dut.u_reg.u_wdog_count_cdc.u_arb

SCORECOND
97.17 93.02
tb.dut.u_reg.u_wkup_cause_cdc.u_arb

TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T2
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T6,T7

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T4,T2
001CoveredT3,T6,T7
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 4 100.00
IF 155 6 6 100.00
CASE 197 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T3,T6,T7
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T4,T2
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T3,T6,T7
0 0 0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T3,T6,T7
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 13116648 4396 0 1680
gen_wr_req.HwIdSelCheck_A 13116648 4703 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13116648 4396 0 1680
T1 6146 4 0 2
T2 237 3 0 3
T3 255111 91 0 3
T4 2978 0 0 2
T5 128268 41 0 3
T6 327660 88 0 3
T7 40743 19 0 3
T8 178434 37 0 3
T9 261 4 0 3
T10 270 3 0 3
T11 8092 29 0 1
T12 76014 5 0 1
T13 0 1 0 0

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13116648 4703 0 0
T1 6146 4 0 0
T2 237 3 0 0
T3 255111 97 0 0
T4 2978 0 0 0
T5 128268 41 0 0
T6 327660 93 0 0
T7 40743 26 0 0
T8 178434 37 0 0
T9 261 5 0 0
T10 270 3 0 0
T11 8092 34 0 0
T12 76014 5 0 0
T13 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504386.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS1396583.33
ALWAYS15510880.00
CONT_ASSIGN18311100.00
ALWAYS187191578.95
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 0 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 0 1
163 1 1
164 0 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 0 1
206 0 1
207 1 1
210 0 1
211 0 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb
TotalCoveredPercent
Conditions433069.77
Logical433069.77
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T5

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT2,T3,T5

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T6,T7
11CoveredT2,T3,T5

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT2,T3,T5

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T2,T3
10CoveredT2,T3,T5

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT3,T6,T7
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11Not Covered

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T4,T2
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T4,T2
001Not Covered
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T2
10Not Covered
11CoveredT1,T2,T3

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T4,T2
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 17 73.91
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 3 75.00
IF 155 6 4 66.67
CASE 197 7 4 57.14

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T2,T3,T5
0 0 1 Covered T2,T3,T5
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T4,T2
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Not Covered
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 3279162 0 0 420
gen_wr_req.HwIdSelCheck_A 3279162 0 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3279162 0 0 420

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3279162 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS1551010100.00
CONT_ASSIGN18311100.00
ALWAYS1871919100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb
TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T2
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT3,T6,T7

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T4,T2
001CoveredT3,T6,T7
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 4 100.00
IF 155 6 6 100.00
CASE 197 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T3,T6,T7
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T4,T2
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T3,T6,T7
0 0 0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T3,T6,T7
StIdle 0 0 0 - Covered T1,T3,T5
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 3279162 2619 0 420
gen_wr_req.HwIdSelCheck_A 3279162 2756 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3279162 2619 0 420
T1 3073 3 0 1
T2 79 1 0 1
T3 85037 61 0 1
T4 1489 0 0 1
T5 42756 25 0 1
T6 109220 57 0 1
T7 13581 9 0 1
T8 59478 22 0 1
T9 87 3 0 1
T10 90 1 0 1
T11 0 18 0 0

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3279162 2756 0 0
T1 3073 3 0 0
T2 79 1 0 0
T3 85037 63 0 0
T4 1489 0 0 0
T5 42756 25 0 0
T6 109220 59 0 0
T7 13581 12 0 0
T8 59478 22 0 0
T9 87 3 0 0
T10 90 1 0 0
T11 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS1551010100.00
CONT_ASSIGN18311100.00
ALWAYS1871919100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb
TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T3
11CoveredT2,T3,T5

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT2,T3,T5

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT2,T3,T5

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT2,T3,T5

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T2,T3
10CoveredT2,T3,T5

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT2,T3,T5

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T4,T2
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT3,T6,T7

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T4,T2
001CoveredT3,T6,T7
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T4,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T3
11CoveredT2,T3,T5

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT2,T3,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 4 100.00
IF 155 6 6 100.00
CASE 197 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T2,T3,T5
0 0 1 Covered T2,T3,T5
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T3,T6,T7
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T4,T2
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T2,T3,T5
0 0 0 0 1 Covered T3,T6,T7
0 0 0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T2,T3,T5
StIdle 0 0 1 - Covered T3,T6,T7
StIdle 0 0 0 - Covered T1,T3,T5
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 3279162 583 0 420
gen_wr_req.HwIdSelCheck_A 3279162 657 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3279162 583 0 420
T2 79 1 0 1
T3 85037 6 0 1
T5 42756 2 0 1
T6 109220 8 0 1
T7 13581 6 0 1
T8 59478 5 0 1
T9 87 0 0 1
T10 90 1 0 1
T11 8092 3 0 1
T12 76014 5 0 1
T13 0 1 0 0

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3279162 657 0 0
T2 79 1 0 0
T3 85037 8 0 0
T5 42756 2 0 0
T6 109220 10 0 0
T7 13581 8 0 0
T8 59478 5 0 0
T9 87 0 0 0
T10 90 1 0 0
T11 8092 5 0 0
T12 76014 5 0 0
T13 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS1551010100.00
CONT_ASSIGN18311100.00
ALWAYS1871919100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb
TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT3,T6,T7
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T7
11CoveredT3,T5,T6

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT3,T5,T6

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T2,T3
10CoveredT3,T5,T6

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T7
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT1,T4,T2
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T6,T7

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T4,T2
001CoveredT3,T6,T7
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 4 100.00
IF 155 6 6 100.00
CASE 197 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T2
0 Covered T1,T4,T2


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T3,T5,T6
0 0 1 Covered T3,T5,T6
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T3,T6,T7
0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T4,T2
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T3,T6,T7
0 0 0 0 0 Covered T1,T4,T2


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T3,T6,T7
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 3279162 1194 0 420
gen_wr_req.HwIdSelCheck_A 3279162 1290 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3279162 1194 0 420
T1 3073 1 0 1
T2 79 1 0 1
T3 85037 24 0 1
T4 1489 0 0 1
T5 42756 14 0 1
T6 109220 23 0 1
T7 13581 4 0 1
T8 59478 10 0 1
T9 87 1 0 1
T10 90 1 0 1
T11 0 8 0 0

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3279162 1290 0 0
T1 3073 1 0 0
T2 79 1 0 0
T3 85037 26 0 0
T4 1489 0 0 0
T5 42756 14 0 0
T6 109220 24 0 0
T7 13581 6 0 0
T8 59478 10 0 0
T9 87 2 0 0
T10 90 1 0 0
T11 0 9 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT2,T3,T5
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT2,T3,T5
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT2,T3,T5
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT2,T3,T5
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T2,T3
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%