Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	719928014	5603715	0	0
wdog_bark_thold_rd_A	719928014	115451	0	0
wdog_bite_thold_rd_A	719928014	102459	0	0
wdog_ctrl_rd_A	719928014	100992	0	0
wdog_regwen_rd_A	719928014	117637	0	0
wkup_ctrl_rd_A	719928014	102237	0	0
wkup_thold_hi_rd_A	719928014	116070	0	0
wkup_thold_lo_rd_A	719928014	101698	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719928014	5603715	0	0
T1	200624	53926	0	0
T2	13706	0	0	0
T3	164712	46605	0	0
T4	195856	0	0	0
T5	978727	0	0	0
T6	922144	247465	0	0
T7	236383	0	0	0
T8	200634	0	0	0
T9	220412	0	0	0
T10	43277	0	0	0
T21	0	213206	0	0
T30	0	41073	0	0
T38	0	174796	0	0
T39	0	73401	0	0
T40	0	98430	0	0
T41	0	98699	0	0
T42	0	199736	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719928014	115451	0	0
T39	349776	7588	0	0
T41	0	9393	0	0
T42	0	20712	0	0
T48	0	8476	0	0
T71	0	7903	0	0
T75	0	5509	0	0
T76	0	3835	0	0
T77	0	6532	0	0
T78	0	17285	0	0
T79	0	5786	0	0
T80	9810	0	0	0
T81	504337	0	0	0
T82	302790	0	0	0
T83	236714	0	0	0
T84	430134	0	0	0
T85	17457	0	0	0
T86	228386	0	0	0
T87	25841	0	0	0
T88	819775	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719928014	102459	0	0
T39	349776	6113	0	0
T41	0	8596	0	0
T42	0	18035	0	0
T48	0	7754	0	0
T71	0	7370	0	0
T75	0	5268	0	0
T76	0	3672	0	0
T77	0	5654	0	0
T78	0	15387	0	0
T79	0	4838	0	0
T80	9810	0	0	0
T81	504337	0	0	0
T82	302790	0	0	0
T83	236714	0	0	0
T84	430134	0	0	0
T85	17457	0	0	0
T86	228386	0	0	0
T87	25841	0	0	0
T88	819775	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719928014	100992	0	0
T39	349776	6285	0	0
T41	0	8438	0	0
T42	0	17774	0	0
T48	0	7245	0	0
T71	0	7037	0	0
T75	0	4787	0	0
T76	0	3665	0	0
T77	0	5519	0	0
T78	0	15151	0	0
T79	0	5045	0	0
T80	9810	0	0	0
T81	504337	0	0	0
T82	302790	0	0	0
T83	236714	0	0	0
T84	430134	0	0	0
T85	17457	0	0	0
T86	228386	0	0	0
T87	25841	0	0	0
T88	819775	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719928014	117637	0	0
T39	349776	7128	0	0
T41	0	9905	0	0
T42	0	20458	0	0
T48	0	8537	0	0
T71	0	8281	0	0
T75	0	6351	0	0
T76	0	3968	0	0
T77	0	6575	0	0
T78	0	17467	0	0
T79	0	5730	0	0
T80	9810	0	0	0
T81	504337	0	0	0
T82	302790	0	0	0
T83	236714	0	0	0
T84	430134	0	0	0
T85	17457	0	0	0
T86	228386	0	0	0
T87	25841	0	0	0
T88	819775	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719928014	102237	0	0
T39	349776	6129	0	0
T41	0	8636	0	0
T42	0	18131	0	0
T48	0	7660	0	0
T71	0	6963	0	0
T75	0	5305	0	0
T76	0	3689	0	0
T77	0	5717	0	0
T78	0	15326	0	0
T79	0	4922	0	0
T80	9810	0	0	0
T81	504337	0	0	0
T82	302790	0	0	0
T83	236714	0	0	0
T84	430134	0	0	0
T85	17457	0	0	0
T86	228386	0	0	0
T87	25841	0	0	0
T88	819775	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719928014	116070	0	0
T39	349776	6793	0	0
T41	0	10011	0	0
T42	0	20348	0	0
T48	0	8476	0	0
T71	0	8029	0	0
T75	0	6127	0	0
T76	0	3913	0	0
T77	0	6404	0	0
T78	0	17036	0	0
T79	0	6084	0	0
T80	9810	0	0	0
T81	504337	0	0	0
T82	302790	0	0	0
T83	236714	0	0	0
T84	430134	0	0	0
T85	17457	0	0	0
T86	228386	0	0	0
T87	25841	0	0	0
T88	819775	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719928014	101698	0	0
T39	349776	6362	0	0
T41	0	9091	0	0
T42	0	18089	0	0
T48	0	7434	0	0
T71	0	6868	0	0
T75	0	4848	0	0
T76	0	3793	0	0
T77	0	5367	0	0
T78	0	14890	0	0
T79	0	5165	0	0
T80	9810	0	0	0
T81	504337	0	0	0
T82	302790	0	0	0
T83	236714	0	0	0
T84	430134	0	0	0
T85	17457	0	0	0
T86	228386	0	0	0
T87	25841	0	0	0
T88	819775	0	0	0