Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.10 94.74 71.83 89.83 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 74.06 92.86 67.35 86.05 50.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.11 100.00 90.14 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.11 100.00 90.14 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.44 100.00 93.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 100.00 90.41 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_ctrl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_thold_hi_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_thold_lo_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORECOND
92.86 71.43
tb.dut.u_reg.u_wkup_count_hi_cdc

SCORECOND
98.21 92.86
tb.dut.u_reg.u_wkup_count_lo_cdc

SCORECOND
98.21 92.86
tb.dut.u_reg.u_wdog_count_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_ctrl_cdc

TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T4

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
98.44 93.75
tb.dut.u_reg.u_wkup_cause_cdc

TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT31,T32,T33

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 2147483647 43947923 0 0
DstReqKnown_A 34235970 33299720 0 0
SrcAckBusyChk_A 2147483647 48298 0 0
SrcBusyKnown_A 2147483647 2147483647 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 43947923 0 0
T1 2006240 169124 0 0
T2 137060 8981 0 0
T3 1647120 134868 0 0
T4 1958560 385552 0 0
T5 9787270 27719 0 0
T6 9221440 1890854 0 0
T7 2363830 94686 0 0
T8 2006340 397742 0 0
T9 2204120 93957 0 0
T10 432770 24147 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34235970 33299720 0 0
T1 85360 84290 0 0
T2 1000 180 0 0
T3 131750 130620 0 0
T4 403800 395620 0 0
T5 20380 19710 0 0
T6 184410 183210 0 0
T7 196970 189850 0 0
T8 41350 35490 0 0
T9 200370 189810 0 0
T10 1030 220 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48298 0 0
T1 2006240 233 0 0
T2 137060 18 0 0
T3 1647120 317 0 0
T4 1958560 213 0 0
T5 9787270 16 0 0
T6 9221440 1104 0 0
T7 2363830 232 0 0
T8 2006340 232 0 0
T9 2204120 253 0 0
T10 432770 15 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 2006240 1999350 0 0
T2 137060 136470 0 0
T3 1647120 1642810 0 0
T4 1958560 1958480 0 0
T5 9787270 9786620 0 0
T6 9221440 9188890 0 0
T7 2363830 2363080 0 0
T8 2006340 2005800 0 0
T9 2204120 2203170 0 0
T10 432770 432210 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 5885588 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 6286 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 5885588 0 0
T1 200624 24152 0 0
T2 13706 1410 0 0
T3 164712 19509 0 0
T4 195856 54980 0 0
T5 978727 3345 0 0
T6 922144 273416 0 0
T7 236383 14079 0 0
T8 200634 61367 0 0
T9 220412 13710 0 0
T10 43277 3231 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 6286 0 0
T1 200624 33 0 0
T2 13706 3 0 0
T3 164712 44 0 0
T4 195856 30 0 0
T5 978727 2 0 0
T6 922144 159 0 0
T7 236383 34 0 0
T8 200634 35 0 0
T9 220412 38 0 0
T10 43277 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 5923333 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 6705 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 5923333 0 0
T1 200624 25635 0 0
T2 13706 933 0 0
T3 164712 19388 0 0
T4 195856 57488 0 0
T5 978727 4778 0 0
T6 922144 259351 0 0
T7 236383 12848 0 0
T8 200634 48308 0 0
T9 220412 12182 0 0
T10 43277 3222 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 6705 0 0
T1 200624 35 0 0
T2 13706 2 0 0
T3 164712 46 0 0
T4 195856 33 0 0
T5 978727 3 0 0
T6 922144 154 0 0
T7 236383 32 0 0
T8 200634 30 0 0
T9 220412 34 0 0
T10 43277 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 2963705 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 3552 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 2963705 0 0
T1 200624 9710 0 0
T2 13706 362 0 0
T3 164712 8102 0 0
T4 195856 21598 0 0
T5 978727 1911 0 0
T6 922144 107425 0 0
T7 236383 4943 0 0
T8 200634 21222 0 0
T9 220412 4970 0 0
T10 43277 1612 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 3552 0 0
T1 200624 15 0 0
T2 13706 1 0 0
T3 164712 21 0 0
T4 195856 13 0 0
T5 978727 1 0 0
T6 922144 69 0 0
T7 236383 14 0 0
T8 200634 14 0 0
T9 220412 15 0 0
T10 43277 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 2946568 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 3524 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 2946568 0 0
T1 200624 9858 0 0
T2 13706 364 0 0
T3 164712 8150 0 0
T4 195856 21624 0 0
T5 978727 1913 0 0
T6 922144 107304 0 0
T7 236383 4971 0 0
T8 200634 20765 0 0
T9 220412 5108 0 0
T10 43277 1625 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 3524 0 0
T1 200624 15 0 0
T2 13706 1 0 0
T3 164712 21 0 0
T4 195856 13 0 0
T5 978727 1 0 0
T6 922144 69 0 0
T7 236383 14 0 0
T8 200634 14 0 0
T9 220412 15 0 0
T10 43277 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 5201724 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 5838 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 5201724 0 0
T1 200624 20201 0 0
T2 13706 928 0 0
T3 164712 16137 0 0
T4 195856 45814 0 0
T5 978727 3352 0 0
T6 922144 226017 0 0
T7 236383 11094 0 0
T8 200634 44536 0 0
T9 220412 10504 0 0
T10 43277 3193 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 5838 0 0
T1 200624 27 0 0
T2 13706 2 0 0
T3 164712 38 0 0
T4 195856 26 0 0
T5 978727 2 0 0
T6 922144 133 0 0
T7 236383 28 0 0
T8 200634 28 0 0
T9 220412 30 0 0
T10 43277 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 2974468 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 3541 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 2974468 0 0
T1 200624 9739 0 0
T2 13706 352 0 0
T3 164712 8174 0 0
T4 195856 21572 0 0
T5 978727 1909 0 0
T6 922144 107072 0 0
T7 236383 5035 0 0
T8 200634 21194 0 0
T9 220412 4940 0 0
T10 43277 1599 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 3541 0 0
T1 200624 15 0 0
T2 13706 1 0 0
T3 164712 21 0 0
T4 195856 13 0 0
T5 978727 1 0 0
T6 922144 69 0 0
T7 236383 14 0 0
T8 200634 14 0 0
T9 220412 15 0 0
T10 43277 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 2910164 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 3500 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 2910164 0 0
T1 200624 9627 0 0
T2 13706 343 0 0
T3 164712 8178 0 0
T4 195856 21546 0 0
T5 978727 1907 0 0
T6 922144 107467 0 0
T7 236383 5007 0 0
T8 200634 21166 0 0
T9 220412 4796 0 0
T10 43277 1587 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 3500 0 0
T1 200624 15 0 0
T2 13706 1 0 0
T3 164712 21 0 0
T4 195856 13 0 0
T5 978727 1 0 0
T6 922144 69 0 0
T7 236383 14 0 0
T8 200634 14 0 0
T9 220412 15 0 0
T10 43277 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 6363732 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 6257 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 6363732 0 0
T1 200624 26854 0 0
T2 13706 1970 0 0
T3 164712 19833 0 0
T4 195856 61827 0 0
T5 978727 3349 0 0
T6 922144 300921 0 0
T7 236383 15342 0 0
T8 200634 69353 0 0
T9 220412 16855 0 0
T10 43277 3244 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 6257 0 0
T1 200624 33 0 0
T2 13706 3 0 0
T3 164712 44 0 0
T4 195856 29 0 0
T5 978727 2 0 0
T6 922144 159 0 0
T7 236383 34 0 0
T8 200634 34 0 0
T9 220412 38 0 0
T10 43277 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T6
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 6000917 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 6263 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 6000917 0 0
T1 200624 24368 0 0
T2 13706 1931 0 0
T3 164712 20050 0 0
T4 195856 54920 0 0
T5 978727 3341 0 0
T6 922144 283597 0 0
T7 236383 15209 0 0
T8 200634 64207 0 0
T9 220412 15332 0 0
T10 43277 3217 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 6263 0 0
T1 200624 33 0 0
T2 13706 3 0 0
T3 164712 44 0 0
T4 195856 30 0 0
T5 978727 2 0 0
T6 922144 159 0 0
T7 236383 34 0 0
T8 200634 35 0 0
T9 220412 38 0 0
T10 43277 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT31,T32,T33

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 719928014 2777724 0 0
DstReqKnown_A 3423597 3329972 0 0
SrcAckBusyChk_A 719928014 2832 0 0
SrcBusyKnown_A 719928014 719231597 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 2777724 0 0
T1 200624 8980 0 0
T2 13706 388 0 0
T3 164712 7347 0 0
T4 195856 24183 0 0
T5 978727 1914 0 0
T6 922144 118284 0 0
T7 236383 6158 0 0
T8 200634 25624 0 0
T9 220412 5560 0 0
T10 43277 1617 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3423597 3329972 0 0
T1 8536 8429 0 0
T2 100 18 0 0
T3 13175 13062 0 0
T4 40380 39562 0 0
T5 2038 1971 0 0
T6 18441 18321 0 0
T7 19697 18985 0 0
T8 4135 3549 0 0
T9 20037 18981 0 0
T10 103 22 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 2832 0 0
T1 200624 12 0 0
T2 13706 1 0 0
T3 164712 17 0 0
T4 195856 13 0 0
T5 978727 1 0 0
T6 922144 64 0 0
T7 236383 14 0 0
T8 200634 14 0 0
T9 220412 15 0 0
T10 43277 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 719928014 719231597 0 0
T1 200624 199935 0 0
T2 13706 13647 0 0
T3 164712 164281 0 0
T4 195856 195848 0 0
T5 978727 978662 0 0
T6 922144 918889 0 0
T7 236383 236308 0 0
T8 200634 200580 0 0
T9 220412 220317 0 0
T10 43277 43221 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%