Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338907	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4160934	1		T1	14		T2	15		T3	261

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1107790	1		T1	1		T2	1		T3	46
values[0x0]	1590158	1		T1	10		T2	11		T3	156
values[0x1]	1801893	1		T1	9		T2	10		T3	183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151998	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4347843	1		T1	14		T2	15		T3	282

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17910	1		T3	3		T5	395		T6	1
valid_sources[0x01]	17146	1		T3	3		T5	528		T6	3
valid_sources[0x02]	18278	1		T3	4		T5	429		T7	3
valid_sources[0x03]	17603	1		T3	1		T5	454		T6	2
valid_sources[0x04]	16493	1		T3	1		T5	425		T7	1
valid_sources[0x05]	18945	1		T3	4		T5	427		T6	1
valid_sources[0x06]	15696	1		T3	1		T5	412		T6	2
valid_sources[0x07]	19792	1		T2	3		T5	362		T6	1
valid_sources[0x08]	18110	1		T3	1		T5	365		T6	2
valid_sources[0x09]	16534	1		T2	3		T3	1		T5	403
valid_sources[0x0a]	16310	1		T3	1		T5	425		T6	4
valid_sources[0x0b]	17049	1		T5	416		T6	3		T8	1
valid_sources[0x0c]	18989	1		T3	3		T5	371		T7	2
valid_sources[0x0d]	17273	1		T3	1		T5	403		T6	2
valid_sources[0x0e]	17551	1		T5	410		T6	1		T7	1
valid_sources[0x0f]	16310	1		T3	4		T5	416		T6	2
valid_sources[0x10]	17744	1		T3	1		T5	459		T7	2
valid_sources[0x11]	17953	1		T3	3		T5	522		T6	1
valid_sources[0x12]	18265	1		T2	2		T3	5		T5	463
valid_sources[0x13]	16689	1		T1	5		T3	2		T5	437
valid_sources[0x14]	18744	1		T3	3		T5	420		T6	3
valid_sources[0x15]	18643	1		T3	2		T5	424		T6	1
valid_sources[0x16]	17659	1		T3	2		T5	522		T6	2
valid_sources[0x17]	16816	1		T5	418		T7	1		T8	1
valid_sources[0x18]	18637	1		T5	400		T6	3		T7	1
valid_sources[0x19]	17850	1		T2	2		T3	1		T5	500
valid_sources[0x1a]	17610	1		T3	3		T5	502		T6	2
valid_sources[0x1b]	18758	1		T1	1		T3	2		T5	362
valid_sources[0x1c]	16782	1		T3	4		T5	445		T6	3
valid_sources[0x1d]	18276	1		T5	482		T8	2		T11	511
valid_sources[0x1e]	16969	1		T3	3		T5	361		T6	1
valid_sources[0x1f]	19583	1		T5	374		T6	1		T11	482
valid_sources[0x20]	16502	1		T5	401		T6	1		T7	2
valid_sources[0x21]	17570	1		T5	368		T6	4		T8	1
valid_sources[0x22]	17873	1		T5	478		T6	3		T7	1
valid_sources[0x23]	19036	1		T3	5		T5	420		T7	1
valid_sources[0x24]	17997	1		T5	497		T6	1		T7	2
valid_sources[0x25]	18536	1		T2	1		T3	4		T5	548
valid_sources[0x26]	17367	1		T5	423		T6	1		T8	2
valid_sources[0x27]	17994	1		T3	2		T5	393		T6	2
valid_sources[0x28]	18803	1		T5	479		T6	1		T11	525
valid_sources[0x29]	17387	1		T5	387		T6	5		T7	2
valid_sources[0x2a]	17190	1		T3	2		T5	507		T6	2
valid_sources[0x2b]	17593	1		T5	425		T6	1		T7	3
valid_sources[0x2c]	18223	1		T3	1		T5	423		T6	1
valid_sources[0x2d]	18114	1		T3	1		T5	446		T6	2
valid_sources[0x2e]	17133	1		T3	1		T5	357		T6	2
valid_sources[0x2f]	18051	1		T5	454		T6	1		T7	3
valid_sources[0x30]	18385	1		T3	2		T5	469		T6	2
valid_sources[0x31]	17466	1		T3	2		T5	478		T6	1
valid_sources[0x32]	17316	1		T5	411		T7	1		T11	438
valid_sources[0x33]	16925	1		T5	367		T6	2		T8	1
valid_sources[0x34]	17836	1		T3	2		T5	491		T8	2
valid_sources[0x35]	16909	1		T3	9		T5	539		T6	2
valid_sources[0x36]	16596	1		T3	2		T5	465		T7	1
valid_sources[0x37]	17106	1		T3	2		T5	477		T8	1
valid_sources[0x38]	16714	1		T5	444		T11	475		T13	515
valid_sources[0x39]	17536	1		T3	2		T5	418		T6	3
valid_sources[0x3a]	18688	1		T3	1		T5	465		T6	2
valid_sources[0x3b]	16548	1		T5	380		T6	2		T7	1
valid_sources[0x3c]	17522	1		T3	3		T5	426		T6	1
valid_sources[0x3d]	17131	1		T5	510		T6	3		T8	1
valid_sources[0x3e]	17428	1		T3	2		T5	451		T6	1
valid_sources[0x3f]	17472	1		T3	1		T5	410		T7	1
valid_sources[0x40]	15818	1		T5	409		T6	1		T8	1
valid_sources[0x41]	18022	1		T3	1		T5	392		T6	1
valid_sources[0x42]	17080	1		T3	1		T5	493		T6	1
valid_sources[0x43]	16027	1		T3	1		T5	433		T7	1
valid_sources[0x44]	18049	1		T1	2		T3	4		T5	437
valid_sources[0x45]	16902	1		T2	3		T5	529		T6	1
valid_sources[0x46]	16159	1		T5	442		T7	1		T11	506
valid_sources[0x47]	17550	1		T3	1		T5	423		T6	1
valid_sources[0x48]	16114	1		T5	470		T6	2		T8	3
valid_sources[0x49]	17887	1		T5	442		T6	1		T7	1
valid_sources[0x4a]	17675	1		T3	1		T5	415		T7	2
valid_sources[0x4b]	16337	1		T3	5		T5	427		T6	3
valid_sources[0x4c]	16245	1		T3	2		T5	449		T7	1
valid_sources[0x4d]	16702	1		T3	1		T5	441		T6	2
valid_sources[0x4e]	16996	1		T3	1		T5	418		T7	2
valid_sources[0x4f]	16650	1		T5	435		T6	3		T7	1
valid_sources[0x50]	17078	1		T3	2		T5	471		T8	2
valid_sources[0x51]	18357	1		T5	426		T11	502		T13	454
valid_sources[0x52]	16009	1		T3	3		T5	436		T6	1
valid_sources[0x53]	18005	1		T5	476		T6	3		T7	2
valid_sources[0x54]	17101	1		T3	2		T5	469		T7	4
valid_sources[0x55]	18695	1		T3	1		T5	521		T6	2
valid_sources[0x56]	15671	1		T3	4		T5	394		T6	2
valid_sources[0x57]	17971	1		T3	3		T5	498		T6	3
valid_sources[0x58]	17694	1		T5	389		T6	2		T7	3
valid_sources[0x59]	16349	1		T3	2		T5	382		T6	2
valid_sources[0x5a]	17493	1		T3	1		T5	430		T6	2
valid_sources[0x5b]	18435	1		T5	394		T6	2		T7	1
valid_sources[0x5c]	16549	1		T3	2		T5	406		T6	7
valid_sources[0x5d]	17621	1		T3	4		T5	383		T7	2
valid_sources[0x5e]	18022	1		T3	1		T5	461		T6	2
valid_sources[0x5f]	16988	1		T3	1		T5	391		T6	1
valid_sources[0x60]	17384	1		T3	6		T5	391		T7	4
valid_sources[0x61]	17127	1		T3	3		T5	444		T7	2
valid_sources[0x62]	18325	1		T3	3		T5	382		T11	491
valid_sources[0x63]	17009	1		T3	1		T5	354		T7	1
valid_sources[0x64]	15260	1		T3	1		T5	417		T6	1
valid_sources[0x65]	17733	1		T2	1		T5	421		T6	1
valid_sources[0x66]	17937	1		T3	2		T5	388		T6	1
valid_sources[0x67]	18079	1		T3	1		T5	473		T6	1
valid_sources[0x68]	16980	1		T3	3		T5	414		T6	3
valid_sources[0x69]	18118	1		T5	452		T6	1		T7	1
valid_sources[0x6a]	16996	1		T3	2		T5	338		T7	4
valid_sources[0x6b]	17555	1		T3	2		T5	523		T7	2
valid_sources[0x6c]	17661	1		T3	3		T5	443		T6	7
valid_sources[0x6d]	17451	1		T5	406		T8	1		T11	505
valid_sources[0x6e]	18087	1		T3	2		T5	390		T6	1
valid_sources[0x6f]	17543	1		T5	463		T6	3		T7	2
valid_sources[0x70]	17145	1		T3	3		T5	458		T6	1
valid_sources[0x71]	18230	1		T3	2		T5	439		T6	3
valid_sources[0x72]	20781	1		T3	1		T5	438		T6	4
valid_sources[0x73]	17482	1		T5	460		T6	1		T7	2
valid_sources[0x74]	17844	1		T3	1		T5	403		T6	1
valid_sources[0x75]	16426	1		T3	1		T5	444		T7	1
valid_sources[0x76]	18524	1		T5	496		T7	1		T8	2
valid_sources[0x77]	17405	1		T5	432		T6	1		T8	3
valid_sources[0x78]	17984	1		T2	1		T3	2		T5	375
valid_sources[0x79]	17543	1		T3	2		T5	525		T6	1
valid_sources[0x7a]	17324	1		T5	456		T6	2		T7	2
valid_sources[0x7b]	18085	1		T3	1		T5	444		T6	5
valid_sources[0x7c]	17653	1		T1	4		T5	403		T6	2
valid_sources[0x7d]	17268	1		T3	1		T5	513		T6	2
valid_sources[0x7e]	17229	1		T3	2		T5	445		T6	2
valid_sources[0x7f]	18252	1		T3	5		T5	501		T8	2
valid_sources[0x80]	15956	1		T3	3		T5	313		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1039283

1

T1

1

T3

23

T4

28

values[0x0]

all_enables

biggest_size

1561445

1

T1

7

T2

8

T3

109

values[0x1]

all_enables

biggest_size

1560206

1

T1

6

T2

7

T3

129