Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	909276998	4901905	0	0
wdog_bark_thold_rd_A	909276998	148737	0	0
wdog_bite_thold_rd_A	909276998	129032	0	0
wdog_ctrl_rd_A	909276998	130066	0	0
wdog_regwen_rd_A	909276998	149867	0	0
wkup_ctrl_rd_A	909276998	130208	0	0
wkup_thold_hi_rd_A	909276998	148546	0	0
wkup_thold_lo_rd_A	909276998	131035	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	909276998	4901905	0	0
T5	494874	122490	0	0
T6	255376	0	0	0
T7	169891	0	0	0
T8	965409	0	0	0
T9	36277	0	0	0
T10	258285	0	0	0
T11	543789	142695	0	0
T12	5635	0	0	0
T13	569674	129129	0	0
T28	0	231637	0	0
T36	0	75258	0	0
T37	0	206134	0	0
T38	0	187540	0	0
T39	0	146751	0	0
T40	0	9027	0	0
T41	0	164778	0	0
T42	41716	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	909276998	148737	0	0
T5	494874	6695	0	0
T6	255376	0	0	0
T7	169891	0	0	0
T8	965409	0	0	0
T9	36277	0	0	0
T10	258285	0	0	0
T11	543789	0	0	0
T12	5635	0	0	0
T13	569674	13858	0	0
T28	0	23439	0	0
T37	0	20452	0	0
T42	41716	0	0	0
T89	0	3907	0	0
T90	0	2981	0	0
T91	0	5628	0	0
T92	0	19252	0	0
T93	0	23400	0	0
T94	0	5149	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	909276998	129032	0	0
T5	494874	5631	0	0
T6	255376	0	0	0
T7	169891	0	0	0
T8	965409	0	0	0
T9	36277	0	0	0
T10	258285	0	0	0
T11	543789	0	0	0
T12	5635	0	0	0
T13	569674	11834	0	0
T28	0	19908	0	0
T37	0	18318	0	0
T42	41716	0	0	0
T89	0	3465	0	0
T90	0	2569	0	0
T91	0	4901	0	0
T92	0	15700	0	0
T93	0	20962	0	0
T94	0	4584	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	909276998	130066	0	0
T5	494874	6165	0	0
T6	255376	0	0	0
T7	169891	0	0	0
T8	965409	0	0	0
T9	36277	0	0	0
T10	258285	0	0	0
T11	543789	0	0	0
T12	5635	0	0	0
T13	569674	11899	0	0
T28	0	20051	0	0
T37	0	18149	0	0
T42	41716	0	0	0
T89	0	3243	0	0
T90	0	2690	0	0
T91	0	5078	0	0
T92	0	16257	0	0
T93	0	20953	0	0
T94	0	4426	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	909276998	149867	0	0
T5	494874	6859	0	0
T6	255376	0	0	0
T7	169891	0	0	0
T8	965409	0	0	0
T9	36277	0	0	0
T10	258285	0	0	0
T11	543789	0	0	0
T12	5635	0	0	0
T13	569674	13627	0	0
T28	0	23410	0	0
T37	0	20685	0	0
T42	41716	0	0	0
T89	0	4262	0	0
T90	0	3193	0	0
T91	0	5668	0	0
T92	0	18438	0	0
T93	0	23680	0	0
T94	0	5290	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	909276998	130208	0	0
T5	494874	5980	0	0
T6	255376	0	0	0
T7	169891	0	0	0
T8	965409	0	0	0
T9	36277	0	0	0
T10	258285	0	0	0
T11	543789	0	0	0
T12	5635	0	0	0
T13	569674	11737	0	0
T28	0	20200	0	0
T37	0	18114	0	0
T42	41716	0	0	0
T89	0	3577	0	0
T90	0	2665	0	0
T91	0	4839	0	0
T92	0	15987	0	0
T93	0	20904	0	0
T94	0	4430	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	909276998	148546	0	0
T5	494874	6835	0	0
T6	255376	0	0	0
T7	169891	0	0	0
T8	965409	0	0	0
T9	36277	0	0	0
T10	258285	0	0	0
T11	543789	0	0	0
T12	5635	0	0	0
T13	569674	13458	0	0
T28	0	24223	0	0
T37	0	20798	0	0
T42	41716	0	0	0
T89	0	3773	0	0
T90	0	3031	0	0
T91	0	5404	0	0
T92	0	17923	0	0
T93	0	23338	0	0
T94	0	5136	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	909276998	131035	0	0
T5	494874	5834	0	0
T6	255376	0	0	0
T7	169891	0	0	0
T8	965409	0	0	0
T9	36277	0	0	0
T10	258285	0	0	0
T11	543789	0	0	0
T12	5635	0	0	0
T13	569674	12238	0	0
T28	0	20509	0	0
T37	0	17955	0	0
T42	41716	0	0	0
T89	0	3716	0	0
T90	0	2702	0	0
T91	0	4718	0	0
T92	0	16106	0	0
T93	0	20883	0	0
T94	0	4282	0	0