Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	749612180	5289840	0	0
wdog_bark_thold_rd_A	749612180	186636	0	0
wdog_bite_thold_rd_A	749612180	162939	0	0
wdog_ctrl_rd_A	749612180	162083	0	0
wdog_regwen_rd_A	749612180	186600	0	0
wkup_ctrl_rd_A	749612180	163474	0	0
wkup_thold_hi_rd_A	749612180	186439	0	0
wkup_thold_lo_rd_A	749612180	163010	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749612180	5289840	0	0
T2	121299	275689	0	0
T3	676466	0	0	0
T4	46210	0	0	0
T5	364514	0	0	0
T6	57107	0	0	0
T7	14441	0	0	0
T8	14435	0	0	0
T9	119968	0	0	0
T10	15603	0	0	0
T11	12821	0	0	0
T12	0	77059	0	0
T14	0	59625	0	0
T25	0	56368	0	0
T34	0	87579	0	0
T41	0	96169	0	0
T42	0	132693	0	0
T43	0	83033	0	0
T44	0	182618	0	0
T45	0	231757	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749612180	186636	0	0
T2	121299	26765	0	0
T3	676466	0	0	0
T4	46210	0	0	0
T5	364514	0	0	0
T6	57107	0	0	0
T7	14441	0	0	0
T8	14435	0	0	0
T9	119968	0	0	0
T10	15603	0	0	0
T11	12821	0	0	0
T12	0	7925	0	0
T14	0	5598	0	0
T41	0	9236	0	0
T42	0	7250	0	0
T44	0	18490	0	0
T92	0	2304	0	0
T98	0	5921	0	0
T99	0	2786	0	0
T100	0	7010	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749612180	162939	0	0
T2	121299	23107	0	0
T3	676466	0	0	0
T4	46210	0	0	0
T5	364514	0	0	0
T6	57107	0	0	0
T7	14441	0	0	0
T8	14435	0	0	0
T9	119968	0	0	0
T10	15603	0	0	0
T11	12821	0	0	0
T12	0	6945	0	0
T14	0	4862	0	0
T41	0	7587	0	0
T42	0	6235	0	0
T44	0	15935	0	0
T92	0	1923	0	0
T98	0	5394	0	0
T99	0	2227	0	0
T100	0	6547	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749612180	162083	0	0
T2	121299	22915	0	0
T3	676466	0	0	0
T4	46210	0	0	0
T5	364514	0	0	0
T6	57107	0	0	0
T7	14441	0	0	0
T8	14435	0	0	0
T9	119968	0	0	0
T10	15603	0	0	0
T11	12821	0	0	0
T12	0	7281	0	0
T14	0	4689	0	0
T41	0	7978	0	0
T42	0	6312	0	0
T44	0	16099	0	0
T92	0	1876	0	0
T98	0	5222	0	0
T99	0	2620	0	0
T100	0	6627	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749612180	186600	0	0
T2	121299	26329	0	0
T3	676466	0	0	0
T4	46210	0	0	0
T5	364514	0	0	0
T6	57107	0	0	0
T7	14441	0	0	0
T8	14435	0	0	0
T9	119968	0	0	0
T10	15603	0	0	0
T11	12821	0	0	0
T12	0	8122	0	0
T14	0	5277	0	0
T41	0	8985	0	0
T42	0	7076	0	0
T44	0	18691	0	0
T92	0	2366	0	0
T98	0	6315	0	0
T99	0	2982	0	0
T100	0	7137	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749612180	163474	0	0
T2	121299	23231	0	0
T3	676466	0	0	0
T4	46210	0	0	0
T5	364514	0	0	0
T6	57107	0	0	0
T7	14441	0	0	0
T8	14435	0	0	0
T9	119968	0	0	0
T10	15603	0	0	0
T11	12821	0	0	0
T12	0	6939	0	0
T14	0	5038	0	0
T41	0	7741	0	0
T42	0	6248	0	0
T44	0	16178	0	0
T92	0	1965	0	0
T98	0	5305	0	0
T99	0	2535	0	0
T100	0	6565	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749612180	186439	0	0
T2	121299	26439	0	0
T3	676466	0	0	0
T4	46210	0	0	0
T5	364514	0	0	0
T6	57107	0	0	0
T7	14441	0	0	0
T8	14435	0	0	0
T9	119968	0	0	0
T10	15603	0	0	0
T11	12821	0	0	0
T12	0	8203	0	0
T14	0	5533	0	0
T41	0	8825	0	0
T42	0	7470	0	0
T44	0	18653	0	0
T92	0	2355	0	0
T98	0	6125	0	0
T99	0	2852	0	0
T100	0	7395	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749612180	163010	0	0
T2	121299	22751	0	0
T3	676466	0	0	0
T4	46210	0	0	0
T5	364514	0	0	0
T6	57107	0	0	0
T7	14441	0	0	0
T8	14435	0	0	0
T9	119968	0	0	0
T10	15603	0	0	0
T11	12821	0	0	0
T12	0	7019	0	0
T14	0	4842	0	0
T41	0	8192	0	0
T42	0	6234	0	0
T44	0	16585	0	0
T92	0	1685	0	0
T98	0	4991	0	0
T99	0	2511	0	0
T100	0	6261	0	0