Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	310843	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3803188	1		T1	112349		T2	14		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1011181	1		T1	29780		T2	1		T3	1
values[0x0]	1456460	1		T1	42670		T2	11		T3	8
values[0x1]	1646390	1		T1	48439		T2	10		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	139739	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3974292	1		T1	117254		T2	15		T3	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14884	1		T1	267		T5	4		T8	1
valid_sources[0x01]	17601	1		T1	1047		T10	1		T46	2
valid_sources[0x02]	15772	1		T1	535		T5	1		T8	1
valid_sources[0x03]	17337	1		T1	900		T5	2		T8	1
valid_sources[0x04]	18145	1		T1	890		T5	1		T6	15
valid_sources[0x05]	15837	1		T1	444		T8	3		T33	2
valid_sources[0x06]	16407	1		T1	353		T5	2		T8	1
valid_sources[0x07]	16017	1		T1	302		T8	3		T33	1
valid_sources[0x08]	14718	1		T1	588		T3	1		T5	1
valid_sources[0x09]	16360	1		T1	677		T12	1		T14	1
valid_sources[0x0a]	15354	1		T1	179		T5	3		T8	4
valid_sources[0x0b]	16444	1		T1	206		T5	3		T8	4
valid_sources[0x0c]	15285	1		T1	603		T8	1		T33	1
valid_sources[0x0d]	15968	1		T1	417		T8	4		T14	2
valid_sources[0x0e]	17330	1		T1	674		T33	2		T16	327
valid_sources[0x0f]	15623	1		T1	406		T8	3		T33	3
valid_sources[0x10]	15865	1		T1	794		T3	1		T8	1
valid_sources[0x11]	16105	1		T1	194		T8	5		T15	1
valid_sources[0x12]	17730	1		T1	367		T3	1		T15	3
valid_sources[0x13]	16687	1		T1	185		T5	1		T8	1
valid_sources[0x14]	14991	1		T1	580		T8	3		T15	1
valid_sources[0x15]	16858	1		T1	586		T5	6		T6	4
valid_sources[0x16]	15816	1		T1	175		T5	2		T8	2
valid_sources[0x17]	15746	1		T1	338		T5	3		T8	1
valid_sources[0x18]	16936	1		T1	782		T6	5		T8	5
valid_sources[0x19]	16583	1		T1	576		T8	2		T14	1
valid_sources[0x1a]	15710	1		T1	471		T15	3		T33	2
valid_sources[0x1b]	16375	1		T1	442		T8	1		T10	1
valid_sources[0x1c]	16622	1		T1	724		T15	1		T16	304
valid_sources[0x1d]	15645	1		T1	351		T5	5		T8	1
valid_sources[0x1e]	15848	1		T1	542		T5	1		T8	2
valid_sources[0x1f]	15822	1		T1	191		T5	2		T8	2
valid_sources[0x20]	16213	1		T1	256		T33	2		T16	300
valid_sources[0x21]	15660	1		T1	186		T3	1		T6	10
valid_sources[0x22]	16246	1		T1	259		T6	9		T8	4
valid_sources[0x23]	14613	1		T1	441		T5	2		T8	6
valid_sources[0x24]	15620	1		T1	605		T5	1		T8	6
valid_sources[0x25]	15362	1		T1	354		T6	13		T8	3
valid_sources[0x26]	15853	1		T1	459		T3	1		T8	3
valid_sources[0x27]	15628	1		T1	215		T5	2		T8	4
valid_sources[0x28]	16337	1		T1	191		T5	4		T8	1
valid_sources[0x29]	16882	1		T1	174		T15	1		T33	3
valid_sources[0x2a]	16038	1		T1	859		T5	1		T8	1
valid_sources[0x2b]	15884	1		T1	349		T5	2		T8	2
valid_sources[0x2c]	17372	1		T1	243		T5	1		T8	2
valid_sources[0x2d]	16979	1		T1	146		T5	1		T8	1
valid_sources[0x2e]	16284	1		T1	300		T5	2		T8	3
valid_sources[0x2f]	15822	1		T1	134		T8	1		T15	1
valid_sources[0x30]	15221	1		T1	496		T5	5		T8	1
valid_sources[0x31]	15848	1		T1	242		T2	2		T8	1
valid_sources[0x32]	15461	1		T1	680		T5	1		T8	3
valid_sources[0x33]	17474	1		T1	599		T5	2		T8	5
valid_sources[0x34]	15234	1		T1	381		T5	2		T8	6
valid_sources[0x35]	15579	1		T1	654		T5	2		T8	1
valid_sources[0x36]	16885	1		T1	568		T33	3		T16	333
valid_sources[0x37]	16085	1		T1	313		T8	1		T12	2
valid_sources[0x38]	15342	1		T1	331		T5	1		T8	4
valid_sources[0x39]	14804	1		T1	347		T5	6		T6	6
valid_sources[0x3a]	17437	1		T1	1124		T5	9		T8	1
valid_sources[0x3b]	14703	1		T1	447		T8	1		T15	3
valid_sources[0x3c]	14920	1		T1	468		T5	1		T6	10
valid_sources[0x3d]	15443	1		T1	745		T16	254		T17	134
valid_sources[0x3e]	17471	1		T1	557		T5	1		T8	1
valid_sources[0x3f]	15670	1		T1	447		T3	1		T6	8
valid_sources[0x40]	16506	1		T1	122		T5	1		T8	2
valid_sources[0x41]	15075	1		T1	168		T8	2		T33	2
valid_sources[0x42]	15202	1		T1	53		T5	1		T6	16
valid_sources[0x43]	15717	1		T1	859		T3	2		T5	4
valid_sources[0x44]	16414	1		T1	347		T5	5		T33	2
valid_sources[0x45]	15238	1		T1	589		T8	1		T15	2
valid_sources[0x46]	16563	1		T1	703		T5	2		T6	7
valid_sources[0x47]	16521	1		T1	898		T5	1		T6	16
valid_sources[0x48]	14804	1		T1	286		T5	1		T8	1
valid_sources[0x49]	17856	1		T1	478		T5	1		T8	2
valid_sources[0x4a]	15833	1		T1	999		T8	2		T33	1
valid_sources[0x4b]	17132	1		T1	618		T5	1		T8	1
valid_sources[0x4c]	15526	1		T1	643		T8	1		T16	336
valid_sources[0x4d]	15696	1		T1	964		T5	1		T15	5
valid_sources[0x4e]	17283	1		T1	263		T5	5		T8	2
valid_sources[0x4f]	14765	1		T1	404		T5	5		T8	7
valid_sources[0x50]	15469	1		T1	371		T5	2		T7	2
valid_sources[0x51]	14529	1		T1	272		T5	4		T8	2
valid_sources[0x52]	14960	1		T1	208		T8	1		T33	1
valid_sources[0x53]	14265	1		T1	435		T5	1		T15	1
valid_sources[0x54]	15512	1		T1	339		T5	3		T15	5
valid_sources[0x55]	16246	1		T1	896		T5	3		T8	1
valid_sources[0x56]	16399	1		T1	54		T5	3		T33	4
valid_sources[0x57]	15991	1		T1	400		T5	2		T8	1
valid_sources[0x58]	15474	1		T1	458		T5	3		T8	2
valid_sources[0x59]	16916	1		T1	479		T3	1		T6	9
valid_sources[0x5a]	14553	1		T1	368		T3	2		T5	1
valid_sources[0x5b]	16415	1		T1	337		T6	2		T8	1
valid_sources[0x5c]	16426	1		T1	596		T10	1		T16	299
valid_sources[0x5d]	17485	1		T1	173		T33	1		T16	365
valid_sources[0x5e]	14732	1		T1	71		T5	4		T8	1
valid_sources[0x5f]	15678	1		T1	511		T6	12		T16	317
valid_sources[0x60]	17209	1		T1	885		T5	1		T8	2
valid_sources[0x61]	16216	1		T1	905		T5	2		T15	4
valid_sources[0x62]	15093	1		T1	63		T5	1		T8	6
valid_sources[0x63]	16208	1		T1	631		T7	2		T8	3
valid_sources[0x64]	17731	1		T1	650		T8	1		T33	1
valid_sources[0x65]	16006	1		T1	341		T5	2		T15	1
valid_sources[0x66]	15387	1		T1	247		T33	2		T16	288
valid_sources[0x67]	15401	1		T1	369		T5	4		T16	314
valid_sources[0x68]	16015	1		T1	350		T8	1		T32	1
valid_sources[0x69]	15741	1		T1	210		T5	1		T6	10
valid_sources[0x6a]	14952	1		T1	550		T5	1		T8	1
valid_sources[0x6b]	16615	1		T1	304		T5	1		T8	2
valid_sources[0x6c]	14876	1		T1	513		T5	1		T6	3
valid_sources[0x6d]	15548	1		T1	307		T8	1		T33	1
valid_sources[0x6e]	15336	1		T1	213		T5	1		T8	1
valid_sources[0x6f]	16291	1		T1	240		T5	2		T8	3
valid_sources[0x70]	16339	1		T1	416		T8	2		T15	2
valid_sources[0x71]	15610	1		T1	132		T33	1		T16	308
valid_sources[0x72]	16250	1		T1	360		T8	5		T14	1
valid_sources[0x73]	16704	1		T1	786		T6	4		T7	2
valid_sources[0x74]	16831	1		T1	494		T5	2		T8	1
valid_sources[0x75]	15359	1		T1	693		T6	29		T8	1
valid_sources[0x76]	15748	1		T1	486		T8	2		T16	333
valid_sources[0x77]	16051	1		T1	661		T8	1		T11	2
valid_sources[0x78]	15446	1		T1	651		T5	1		T8	4
valid_sources[0x79]	14900	1		T1	592		T5	4		T15	1
valid_sources[0x7a]	15359	1		T1	543		T5	1		T9	2
valid_sources[0x7b]	15259	1		T1	55		T15	3		T33	1
valid_sources[0x7c]	17816	1		T1	199		T5	1		T15	3
valid_sources[0x7d]	16855	1		T1	461		T5	2		T8	4
valid_sources[0x7e]	16181	1		T1	404		T6	27		T8	2
valid_sources[0x7f]	14498	1		T1	363		T5	4		T33	1
valid_sources[0x80]	14726	1		T1	488		T5	2		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

947562

1

T1

28106

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1429484

1

T1

42062

T2

8

T3

7

values[0x1]

all_enables

biggest_size

1426142

1

T1

42181

T2

5

T3

6