Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	789901543	4477142	0	0
wdog_bark_thold_rd_A	789901543	132908	0	0
wdog_bite_thold_rd_A	789901543	115576	0	0
wdog_ctrl_rd_A	789901543	114994	0	0
wdog_regwen_rd_A	789901543	131449	0	0
wkup_ctrl_rd_A	789901543	115615	0	0
wkup_thold_hi_rd_A	789901543	132213	0	0
wkup_thold_lo_rd_A	789901543	115269	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789901543	4477142	0	0
T1	624248	127935	0	0
T2	8535	0	0	0
T3	41919	0	0	0
T4	621289	0	0	0
T5	276352	0	0	0
T6	133643	0	0	0
T7	390871	0	0	0
T8	288263	0	0	0
T9	28790	0	0	0
T10	9933	0	0	0
T16	0	87687	0	0
T17	0	37843	0	0
T26	0	78903	0	0
T40	0	94315	0	0
T41	0	61652	0	0
T42	0	98487	0	0
T43	0	216004	0	0
T44	0	69496	0	0
T45	0	121244	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789901543	132908	0	0
T1	624248	13000	0	0
T2	8535	0	0	0
T3	41919	0	0	0
T4	621289	0	0	0
T5	276352	0	0	0
T6	133643	0	0	0
T7	390871	0	0	0
T8	288263	0	0	0
T9	28790	0	0	0
T10	9933	0	0	0
T17	0	4164	0	0
T26	0	7496	0	0
T42	0	10008	0	0
T44	0	6954	0	0
T83	0	4939	0	0
T86	0	2125	0	0
T90	0	6493	0	0
T91	0	7032	0	0
T92	0	11499	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789901543	115576	0	0
T1	624248	11204	0	0
T2	8535	0	0	0
T3	41919	0	0	0
T4	621289	0	0	0
T5	276352	0	0	0
T6	133643	0	0	0
T7	390871	0	0	0
T8	288263	0	0	0
T9	28790	0	0	0
T10	9933	0	0	0
T17	0	3491	0	0
T26	0	6286	0	0
T42	0	8916	0	0
T44	0	5765	0	0
T83	0	4480	0	0
T86	0	1826	0	0
T90	0	5728	0	0
T91	0	5888	0	0
T92	0	9869	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789901543	114994	0	0
T1	624248	11678	0	0
T2	8535	0	0	0
T3	41919	0	0	0
T4	621289	0	0	0
T5	276352	0	0	0
T6	133643	0	0	0
T7	390871	0	0	0
T8	288263	0	0	0
T9	28790	0	0	0
T10	9933	0	0	0
T17	0	3683	0	0
T26	0	6409	0	0
T42	0	9358	0	0
T44	0	6107	0	0
T83	0	3965	0	0
T86	0	1739	0	0
T90	0	5454	0	0
T91	0	5862	0	0
T92	0	9709	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789901543	131449	0	0
T1	624248	12357	0	0
T2	8535	0	0	0
T3	41919	0	0	0
T4	621289	0	0	0
T5	276352	0	0	0
T6	133643	0	0	0
T7	390871	0	0	0
T8	288263	0	0	0
T9	28790	0	0	0
T10	9933	0	0	0
T17	0	4080	0	0
T26	0	7368	0	0
T42	0	9838	0	0
T44	0	7049	0	0
T83	0	4938	0	0
T86	0	2106	0	0
T90	0	6450	0	0
T91	0	6675	0	0
T92	0	11465	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789901543	115615	0	0
T1	624248	11308	0	0
T2	8535	0	0	0
T3	41919	0	0	0
T4	621289	0	0	0
T5	276352	0	0	0
T6	133643	0	0	0
T7	390871	0	0	0
T8	288263	0	0	0
T9	28790	0	0	0
T10	9933	0	0	0
T17	0	3642	0	0
T26	0	6276	0	0
T42	0	8803	0	0
T44	0	6012	0	0
T83	0	4293	0	0
T86	0	1717	0	0
T90	0	5529	0	0
T91	0	5865	0	0
T92	0	10316	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789901543	132213	0	0
T1	624248	12961	0	0
T2	8535	0	0	0
T3	41919	0	0	0
T4	621289	0	0	0
T5	276352	0	0	0
T6	133643	0	0	0
T7	390871	0	0	0
T8	288263	0	0	0
T9	28790	0	0	0
T10	9933	0	0	0
T17	0	4300	0	0
T26	0	7418	0	0
T42	0	10186	0	0
T44	0	6790	0	0
T83	0	4853	0	0
T86	0	2002	0	0
T90	0	6415	0	0
T91	0	6893	0	0
T92	0	11236	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789901543	115269	0	0
T1	624248	11298	0	0
T2	8535	0	0	0
T3	41919	0	0	0
T4	621289	0	0	0
T5	276352	0	0	0
T6	133643	0	0	0
T7	390871	0	0	0
T8	288263	0	0	0
T9	28790	0	0	0
T10	9933	0	0	0
T17	0	3488	0	0
T26	0	6162	0	0
T42	0	9272	0	0
T44	0	6514	0	0
T83	0	4059	0	0
T86	0	1597	0	0
T90	0	5695	0	0
T91	0	5812	0	0
T92	0	9678	0	0