Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	331472	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4030544	1		T1	71144		T2	13		T3	16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1073018	1		T1	18912		T2	1		T3	1
values[0x0]	1542005	1		T1	27174		T2	9		T3	10
values[0x1]	1746993	1		T1	30459		T2	10		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148845	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4213171	1		T1	74167		T2	14		T3	18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17480	1		T1	303		T5	1056		T8	4
valid_sources[0x01]	17019	1		T1	284		T5	693		T7	19
valid_sources[0x02]	17546	1		T1	274		T5	871		T10	177
valid_sources[0x03]	17125	1		T1	243		T5	291		T10	190
valid_sources[0x04]	17508	1		T1	295		T5	938		T8	15
valid_sources[0x05]	18058	1		T1	239		T5	999		T9	1
valid_sources[0x06]	15905	1		T1	352		T5	296		T10	193
valid_sources[0x07]	17288	1		T1	329		T5	854		T8	5
valid_sources[0x08]	17641	1		T1	378		T5	540		T10	167
valid_sources[0x09]	16840	1		T1	299		T5	919		T10	206
valid_sources[0x0a]	16525	1		T1	250		T4	2		T5	604
valid_sources[0x0b]	17351	1		T1	366		T5	1465		T10	188
valid_sources[0x0c]	18140	1		T1	359		T5	888		T10	211
valid_sources[0x0d]	17481	1		T1	349		T5	1104		T10	193
valid_sources[0x0e]	16232	1		T1	340		T5	419		T10	195
valid_sources[0x0f]	17254	1		T1	299		T5	613		T10	191
valid_sources[0x10]	16687	1		T1	329		T5	879		T8	1
valid_sources[0x11]	17106	1		T1	305		T5	610		T10	204
valid_sources[0x12]	16471	1		T1	297		T5	1128		T10	217
valid_sources[0x13]	17464	1		T1	282		T4	3		T5	909
valid_sources[0x14]	15499	1		T1	263		T2	1		T5	491
valid_sources[0x15]	16102	1		T1	285		T5	402		T10	177
valid_sources[0x16]	17198	1		T1	263		T4	3		T5	554
valid_sources[0x17]	18083	1		T1	339		T5	948		T10	195
valid_sources[0x18]	16954	1		T1	247		T5	744		T8	3
valid_sources[0x19]	17708	1		T1	283		T5	626		T8	6
valid_sources[0x1a]	16856	1		T1	277		T5	1051		T10	190
valid_sources[0x1b]	18333	1		T1	318		T2	1		T5	474
valid_sources[0x1c]	17286	1		T1	369		T5	1303		T10	193
valid_sources[0x1d]	16431	1		T1	355		T5	505		T10	172
valid_sources[0x1e]	16016	1		T1	235		T5	614		T8	2
valid_sources[0x1f]	16177	1		T1	329		T5	680		T10	161
valid_sources[0x20]	16549	1		T1	326		T5	562		T10	204
valid_sources[0x21]	17405	1		T1	336		T5	827		T8	9
valid_sources[0x22]	16233	1		T1	320		T5	605		T10	216
valid_sources[0x23]	16020	1		T1	356		T2	1		T5	191
valid_sources[0x24]	16650	1		T1	293		T5	228		T8	1
valid_sources[0x25]	17621	1		T1	250		T5	473		T8	4
valid_sources[0x26]	17403	1		T1	273		T5	626		T10	219
valid_sources[0x27]	17155	1		T1	302		T5	1137		T10	198
valid_sources[0x28]	16778	1		T1	354		T5	810		T10	180
valid_sources[0x29]	16711	1		T1	301		T5	587		T8	4
valid_sources[0x2a]	16666	1		T1	276		T5	607		T10	162
valid_sources[0x2b]	17901	1		T1	356		T5	493		T8	2
valid_sources[0x2c]	16852	1		T1	269		T5	871		T10	160
valid_sources[0x2d]	16311	1		T1	370		T5	395		T10	191
valid_sources[0x2e]	16981	1		T1	367		T5	548		T10	186
valid_sources[0x2f]	15429	1		T1	287		T2	1		T5	293
valid_sources[0x30]	17713	1		T1	342		T5	667		T10	173
valid_sources[0x31]	16752	1		T1	379		T5	383		T8	1
valid_sources[0x32]	17293	1		T1	326		T5	548		T10	195
valid_sources[0x33]	15996	1		T1	220		T5	806		T10	190
valid_sources[0x34]	17177	1		T1	356		T5	333		T8	3
valid_sources[0x35]	17295	1		T1	265		T5	512		T8	2
valid_sources[0x36]	17212	1		T1	248		T2	1		T5	781
valid_sources[0x37]	17276	1		T1	359		T5	445		T8	3
valid_sources[0x38]	16822	1		T1	259		T5	692		T10	202
valid_sources[0x39]	17120	1		T1	352		T2	1		T5	645
valid_sources[0x3a]	16288	1		T1	236		T4	1		T5	706
valid_sources[0x3b]	19426	1		T1	340		T5	947		T10	213
valid_sources[0x3c]	17370	1		T1	281		T5	603		T8	3
valid_sources[0x3d]	17275	1		T1	278		T5	1205		T8	3
valid_sources[0x3e]	16817	1		T1	373		T2	2		T5	486
valid_sources[0x3f]	16784	1		T1	375		T5	419		T10	182
valid_sources[0x40]	16721	1		T1	293		T5	523		T10	187
valid_sources[0x41]	17208	1		T1	300		T5	1092		T8	2
valid_sources[0x42]	16424	1		T1	291		T5	884		T10	182
valid_sources[0x43]	16770	1		T1	289		T5	1105		T10	204
valid_sources[0x44]	17158	1		T1	260		T5	504		T10	190
valid_sources[0x45]	17018	1		T1	263		T5	335		T8	3
valid_sources[0x46]	18105	1		T1	368		T5	919		T10	196
valid_sources[0x47]	17106	1		T1	343		T4	1		T5	875
valid_sources[0x48]	17527	1		T1	356		T2	1		T5	818
valid_sources[0x49]	17047	1		T1	304		T5	775		T10	212
valid_sources[0x4a]	16280	1		T1	256		T5	604		T10	231
valid_sources[0x4b]	17252	1		T1	318		T5	648		T10	181
valid_sources[0x4c]	15831	1		T1	307		T5	555		T10	198
valid_sources[0x4d]	17115	1		T1	280		T5	473		T8	2
valid_sources[0x4e]	16710	1		T1	283		T5	963		T8	10
valid_sources[0x4f]	19099	1		T1	264		T5	733		T10	193
valid_sources[0x50]	16685	1		T1	270		T5	420		T10	195
valid_sources[0x51]	17875	1		T1	319		T2	1		T5	636
valid_sources[0x52]	17549	1		T1	317		T4	1		T5	957
valid_sources[0x53]	17456	1		T1	374		T5	297		T10	164
valid_sources[0x54]	16230	1		T1	285		T5	54		T10	212
valid_sources[0x55]	17024	1		T1	335		T5	574		T10	188
valid_sources[0x56]	16728	1		T1	306		T5	627		T8	6
valid_sources[0x57]	16791	1		T1	380		T5	481		T9	3
valid_sources[0x58]	16753	1		T1	292		T5	657		T10	197
valid_sources[0x59]	16199	1		T1	290		T5	240		T10	196
valid_sources[0x5a]	16658	1		T1	268		T5	1156		T9	1
valid_sources[0x5b]	17041	1		T1	286		T5	713		T10	224
valid_sources[0x5c]	18183	1		T1	274		T5	955		T8	1
valid_sources[0x5d]	17131	1		T1	323		T5	703		T10	211
valid_sources[0x5e]	15865	1		T1	215		T5	391		T10	208
valid_sources[0x5f]	17045	1		T1	256		T5	975		T10	198
valid_sources[0x60]	16206	1		T1	241		T5	991		T10	184
valid_sources[0x61]	16241	1		T1	327		T5	829		T10	192
valid_sources[0x62]	17581	1		T1	322		T5	561		T10	213
valid_sources[0x63]	16334	1		T1	340		T5	742		T8	1
valid_sources[0x64]	17257	1		T1	207		T5	1005		T10	194
valid_sources[0x65]	16486	1		T1	281		T5	1043		T8	5
valid_sources[0x66]	16311	1		T1	301		T5	233		T10	203
valid_sources[0x67]	15620	1		T1	276		T2	1		T5	460
valid_sources[0x68]	16980	1		T1	214		T2	2		T5	104
valid_sources[0x69]	16353	1		T1	295		T5	701		T8	2
valid_sources[0x6a]	18496	1		T1	335		T4	1		T5	927
valid_sources[0x6b]	17090	1		T1	254		T5	444		T10	203
valid_sources[0x6c]	16880	1		T1	313		T5	780		T10	231
valid_sources[0x6d]	17237	1		T1	360		T5	946		T8	7
valid_sources[0x6e]	17433	1		T1	269		T5	410		T9	2
valid_sources[0x6f]	17250	1		T1	310		T5	1189		T8	1
valid_sources[0x70]	17356	1		T1	307		T5	1093		T8	1
valid_sources[0x71]	17665	1		T1	276		T5	261		T8	1
valid_sources[0x72]	16028	1		T1	243		T5	439		T9	1
valid_sources[0x73]	18124	1		T1	394		T5	510		T9	1
valid_sources[0x74]	16407	1		T1	353		T5	583		T8	1
valid_sources[0x75]	17415	1		T1	305		T5	962		T10	195
valid_sources[0x76]	17549	1		T1	239		T5	330		T8	8
valid_sources[0x77]	17011	1		T1	331		T5	600		T10	179
valid_sources[0x78]	17852	1		T1	294		T5	1193		T8	1
valid_sources[0x79]	15829	1		T1	264		T5	657		T10	198
valid_sources[0x7a]	15933	1		T1	214		T5	464		T10	227
valid_sources[0x7b]	16473	1		T1	310		T5	368		T10	164
valid_sources[0x7c]	17114	1		T1	227		T5	554		T8	7
valid_sources[0x7d]	16533	1		T1	304		T5	878		T10	206
valid_sources[0x7e]	16429	1		T1	254		T5	709		T8	4
valid_sources[0x7f]	16966	1		T1	260		T5	817		T8	3
valid_sources[0x80]	17620	1		T1	204		T5	572		T10	192

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1005374

1

T1

17799

T3

1

T5

39697

values[0x0]

all_enables

biggest_size

1513949

1

T1

26758

T2

7

T3

9

values[0x1]

all_enables

biggest_size

1511221

1

T1

26587

T2

6

T3

6