Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	767242031	4798497	0	0
wdog_bark_thold_rd_A	767242031	110747	0	0
wdog_bite_thold_rd_A	767242031	96364	0	0
wdog_ctrl_rd_A	767242031	97671	0	0
wdog_regwen_rd_A	767242031	110285	0	0
wkup_ctrl_rd_A	767242031	97167	0	0
wkup_thold_hi_rd_A	767242031	110674	0	0
wkup_thold_lo_rd_A	767242031	96553	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	767242031	4798497	0	0
T1	421136	81460	0	0
T2	120907	0	0	0
T3	184363	0	0	0
T4	13635	0	0	0
T5	837243	189083	0	0
T6	35872	0	0	0
T7	28940	0	0	0
T8	348769	0	0	0
T9	107707	0	0	0
T10	240106	52466	0	0
T21	0	45758	0	0
T25	0	126919	0	0
T31	0	69808	0	0
T32	0	58784	0	0
T40	0	137079	0	0
T41	0	92746	0	0
T42	0	61074	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	767242031	110747	0	0
T1	421136	8534	0	0
T2	120907	0	0	0
T3	184363	0	0	0
T4	13635	0	0	0
T5	837243	18234	0	0
T6	35872	0	0	0
T7	28940	0	0	0
T8	348769	0	0	0
T9	107707	0	0	0
T10	240106	5122	0	0
T21	0	4646	0	0
T31	0	3659	0	0
T42	0	6376	0	0
T47	0	3803	0	0
T70	0	18713	0	0
T71	0	10923	0	0
T72	0	2656	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	767242031	96364	0	0
T1	421136	7344	0	0
T2	120907	0	0	0
T3	184363	0	0	0
T4	13635	0	0	0
T5	837243	15725	0	0
T6	35872	0	0	0
T7	28940	0	0	0
T8	348769	0	0	0
T9	107707	0	0	0
T10	240106	4684	0	0
T21	0	4237	0	0
T31	0	3391	0	0
T42	0	5048	0	0
T47	0	3234	0	0
T70	0	16544	0	0
T71	0	9704	0	0
T72	0	2405	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	767242031	97671	0	0
T1	421136	7126	0	0
T2	120907	0	0	0
T3	184363	0	0	0
T4	13635	0	0	0
T5	837243	15481	0	0
T6	35872	0	0	0
T7	28940	0	0	0
T8	348769	0	0	0
T9	107707	0	0	0
T10	240106	4803	0	0
T21	0	3937	0	0
T31	0	3249	0	0
T42	0	5782	0	0
T47	0	3325	0	0
T70	0	17029	0	0
T71	0	9764	0	0
T72	0	2229	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	767242031	110285	0	0
T1	421136	8291	0	0
T2	120907	0	0	0
T3	184363	0	0	0
T4	13635	0	0	0
T5	837243	18609	0	0
T6	35872	0	0	0
T7	28940	0	0	0
T8	348769	0	0	0
T9	107707	0	0	0
T10	240106	5595	0	0
T21	0	4357	0	0
T31	0	3610	0	0
T42	0	6105	0	0
T47	0	3614	0	0
T70	0	19120	0	0
T71	0	10803	0	0
T72	0	2679	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	767242031	97167	0	0
T1	421136	6839	0	0
T2	120907	0	0	0
T3	184363	0	0	0
T4	13635	0	0	0
T5	837243	16461	0	0
T6	35872	0	0	0
T7	28940	0	0	0
T8	348769	0	0	0
T9	107707	0	0	0
T10	240106	4599	0	0
T21	0	3734	0	0
T31	0	3322	0	0
T42	0	5656	0	0
T47	0	3204	0	0
T70	0	16768	0	0
T71	0	9341	0	0
T72	0	2142	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	767242031	110674	0	0
T1	421136	7863	0	0
T2	120907	0	0	0
T3	184363	0	0	0
T4	13635	0	0	0
T5	837243	17721	0	0
T6	35872	0	0	0
T7	28940	0	0	0
T8	348769	0	0	0
T9	107707	0	0	0
T10	240106	5797	0	0
T21	0	4621	0	0
T31	0	3672	0	0
T42	0	6333	0	0
T47	0	3577	0	0
T70	0	19200	0	0
T71	0	11067	0	0
T72	0	2808	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	767242031	96553	0	0
T1	421136	7164	0	0
T2	120907	0	0	0
T3	184363	0	0	0
T4	13635	0	0	0
T5	837243	15729	0	0
T6	35872	0	0	0
T7	28940	0	0	0
T8	348769	0	0	0
T9	107707	0	0	0
T10	240106	4654	0	0
T21	0	3630	0	0
T31	0	3437	0	0
T42	0	5299	0	0
T47	0	3474	0	0
T70	0	16943	0	0
T71	0	9754	0	0
T72	0	2386	0	0