Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	306832	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3713911	1		T1	13		T2	11		T3	13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	987364	1		T1	1		T2	1		T3	1
values[0x0]	1421702	1		T1	13		T2	8		T3	10
values[0x1]	1611677	1		T1	6		T2	11		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	138300	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3882443	1		T1	16		T2	11		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15221	1		T4	155		T8	252		T10	239
valid_sources[0x01]	16751	1		T4	223		T8	224		T10	226
valid_sources[0x02]	16034	1		T4	199		T7	5		T8	215
valid_sources[0x03]	17590	1		T4	211		T8	213		T10	243
valid_sources[0x04]	16654	1		T4	239		T7	2		T8	296
valid_sources[0x05]	14727	1		T4	194		T8	255		T10	236
valid_sources[0x06]	15394	1		T4	216		T7	1		T8	231
valid_sources[0x07]	14607	1		T4	196		T8	314		T10	239
valid_sources[0x08]	14673	1		T4	214		T8	215		T10	246
valid_sources[0x09]	15551	1		T4	215		T8	253		T10	260
valid_sources[0x0a]	14879	1		T4	187		T6	1		T8	214
valid_sources[0x0b]	15906	1		T4	222		T7	6		T8	287
valid_sources[0x0c]	14192	1		T3	1		T4	221		T8	322
valid_sources[0x0d]	14315	1		T4	227		T8	230		T10	226
valid_sources[0x0e]	16684	1		T4	216		T8	228		T10	238
valid_sources[0x0f]	16787	1		T4	193		T8	236		T10	247
valid_sources[0x10]	15319	1		T2	20		T4	214		T8	275
valid_sources[0x11]	13783	1		T4	214		T8	277		T10	260
valid_sources[0x12]	17044	1		T4	227		T6	1		T7	2
valid_sources[0x13]	17186	1		T4	256		T6	1		T7	2
valid_sources[0x14]	15090	1		T4	246		T8	272		T10	240
valid_sources[0x15]	15062	1		T3	1		T4	214		T7	1
valid_sources[0x16]	15107	1		T4	247		T6	1		T8	284
valid_sources[0x17]	18850	1		T4	203		T7	3		T8	240
valid_sources[0x18]	15468	1		T4	180		T7	4		T8	313
valid_sources[0x19]	16279	1		T4	198		T7	2		T8	272
valid_sources[0x1a]	16653	1		T3	1		T4	235		T7	3
valid_sources[0x1b]	15480	1		T4	239		T7	4		T8	235
valid_sources[0x1c]	15970	1		T4	211		T8	272		T10	266
valid_sources[0x1d]	15455	1		T4	185		T8	241		T10	256
valid_sources[0x1e]	14633	1		T4	211		T7	1		T8	279
valid_sources[0x1f]	14308	1		T4	283		T8	246		T9	3
valid_sources[0x20]	14798	1		T4	186		T7	1		T8	223
valid_sources[0x21]	17624	1		T4	239		T7	3		T8	230
valid_sources[0x22]	15707	1		T4	226		T8	210		T10	231
valid_sources[0x23]	14730	1		T4	206		T8	229		T10	266
valid_sources[0x24]	16204	1		T4	244		T7	1		T8	235
valid_sources[0x25]	15432	1		T4	240		T7	1		T8	224
valid_sources[0x26]	15781	1		T4	188		T8	258		T10	269
valid_sources[0x27]	15426	1		T4	194		T8	233		T10	260
valid_sources[0x28]	15950	1		T4	267		T8	270		T10	233
valid_sources[0x29]	16564	1		T4	242		T7	3		T8	307
valid_sources[0x2a]	13920	1		T4	185		T8	255		T10	238
valid_sources[0x2b]	13796	1		T4	224		T8	259		T10	261
valid_sources[0x2c]	15382	1		T4	197		T8	264		T10	232
valid_sources[0x2d]	15590	1		T4	235		T8	239		T10	255
valid_sources[0x2e]	15724	1		T4	176		T7	2		T8	202
valid_sources[0x2f]	15360	1		T4	202		T8	260		T10	286
valid_sources[0x30]	15118	1		T1	7		T4	213		T6	1
valid_sources[0x31]	15806	1		T4	211		T8	300		T10	298
valid_sources[0x32]	16188	1		T4	218		T7	6		T8	289
valid_sources[0x33]	16256	1		T4	218		T8	191		T10	222
valid_sources[0x34]	15957	1		T4	191		T7	1		T8	207
valid_sources[0x35]	16399	1		T4	204		T8	215		T10	243
valid_sources[0x36]	14235	1		T4	247		T7	4		T8	167
valid_sources[0x37]	15524	1		T4	204		T8	238		T10	250
valid_sources[0x38]	14786	1		T4	237		T8	287		T10	221
valid_sources[0x39]	15794	1		T4	218		T8	287		T10	267
valid_sources[0x3a]	14464	1		T4	205		T7	1		T8	240
valid_sources[0x3b]	14909	1		T4	179		T8	246		T10	257
valid_sources[0x3c]	15960	1		T4	185		T8	268		T10	222
valid_sources[0x3d]	15521	1		T4	187		T7	4		T8	209
valid_sources[0x3e]	16185	1		T4	263		T8	295		T10	258
valid_sources[0x3f]	15821	1		T4	185		T7	7		T8	258
valid_sources[0x40]	16511	1		T4	260		T8	162		T10	249
valid_sources[0x41]	16871	1		T4	195		T6	1		T8	204
valid_sources[0x42]	14382	1		T4	195		T7	3		T8	206
valid_sources[0x43]	16223	1		T4	201		T7	6		T8	193
valid_sources[0x44]	16016	1		T4	243		T6	1		T8	225
valid_sources[0x45]	15766	1		T3	2		T4	206		T6	1
valid_sources[0x46]	15902	1		T4	180		T7	1		T8	238
valid_sources[0x47]	16592	1		T4	218		T7	1		T8	306
valid_sources[0x48]	14972	1		T3	1		T4	195		T6	1
valid_sources[0x49]	14724	1		T4	253		T7	5		T8	293
valid_sources[0x4a]	16378	1		T4	223		T7	6		T8	296
valid_sources[0x4b]	16113	1		T4	228		T7	2		T8	229
valid_sources[0x4c]	15169	1		T4	217		T8	240		T10	253
valid_sources[0x4d]	16676	1		T4	188		T7	2		T8	302
valid_sources[0x4e]	15159	1		T4	216		T7	3		T8	265
valid_sources[0x4f]	15849	1		T3	3		T4	207		T7	13
valid_sources[0x50]	15883	1		T4	198		T7	7		T8	259
valid_sources[0x51]	15422	1		T4	245		T7	8		T8	188
valid_sources[0x52]	15880	1		T4	178		T8	228		T10	234
valid_sources[0x53]	15442	1		T4	195		T6	1		T7	5
valid_sources[0x54]	14579	1		T4	222		T7	4		T8	238
valid_sources[0x55]	13341	1		T4	218		T7	1		T8	253
valid_sources[0x56]	14082	1		T4	268		T7	1		T8	206
valid_sources[0x57]	15845	1		T4	228		T8	249		T10	280
valid_sources[0x58]	16346	1		T4	234		T8	225		T10	268
valid_sources[0x59]	16380	1		T4	239		T7	1		T8	238
valid_sources[0x5a]	15524	1		T4	213		T7	2		T8	266
valid_sources[0x5b]	14484	1		T4	187		T7	4		T8	194
valid_sources[0x5c]	15177	1		T4	267		T7	1		T8	328
valid_sources[0x5d]	16461	1		T4	215		T7	1		T8	247
valid_sources[0x5e]	14869	1		T4	218		T8	223		T10	264
valid_sources[0x5f]	15938	1		T4	186		T8	284		T10	260
valid_sources[0x60]	16519	1		T4	179		T7	5		T8	325
valid_sources[0x61]	16260	1		T4	234		T7	1		T8	309
valid_sources[0x62]	15577	1		T4	191		T8	222		T10	253
valid_sources[0x63]	16729	1		T4	236		T8	162		T10	303
valid_sources[0x64]	17266	1		T4	198		T8	255		T10	245
valid_sources[0x65]	15158	1		T3	2		T4	225		T7	3
valid_sources[0x66]	16726	1		T4	222		T7	1		T8	242
valid_sources[0x67]	15836	1		T4	207		T8	266		T10	266
valid_sources[0x68]	16105	1		T4	226		T6	1		T8	249
valid_sources[0x69]	15863	1		T4	238		T6	1		T8	258
valid_sources[0x6a]	16030	1		T4	229		T8	222		T10	273
valid_sources[0x6b]	14638	1		T1	13		T4	237		T8	217
valid_sources[0x6c]	17253	1		T4	203		T7	4		T8	244
valid_sources[0x6d]	15798	1		T4	179		T7	3		T8	250
valid_sources[0x6e]	14917	1		T4	174		T8	254		T10	265
valid_sources[0x6f]	14039	1		T4	222		T8	265		T10	246
valid_sources[0x70]	17635	1		T4	207		T8	244		T10	225
valid_sources[0x71]	14836	1		T4	205		T7	2		T8	243
valid_sources[0x72]	14846	1		T4	184		T8	212		T10	238
valid_sources[0x73]	14737	1		T4	212		T8	192		T10	252
valid_sources[0x74]	15034	1		T4	177		T8	196		T10	261
valid_sources[0x75]	16787	1		T4	195		T7	4		T8	246
valid_sources[0x76]	16257	1		T4	230		T7	6		T8	188
valid_sources[0x77]	16707	1		T4	198		T7	3		T8	220
valid_sources[0x78]	18156	1		T3	1		T4	198		T8	244
valid_sources[0x79]	14795	1		T4	215		T8	207		T9	1
valid_sources[0x7a]	16159	1		T4	266		T8	270		T10	270
valid_sources[0x7b]	15306	1		T4	201		T8	222		T10	241
valid_sources[0x7c]	17479	1		T4	218		T7	1		T8	199
valid_sources[0x7d]	14880	1		T4	255		T7	1		T8	298
valid_sources[0x7e]	15921	1		T4	203		T8	232		T10	236
valid_sources[0x7f]	15393	1		T4	220		T7	2		T8	211
valid_sources[0x80]	15513	1		T4	236		T7	2		T8	247

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

924620

1

T1

1

T4

12480

T7

29

values[0x0]

all_enables

biggest_size

1395264

1

T1

9

T2

3

T3

8

values[0x1]

all_enables

biggest_size

1394027

1

T1

3

T2

8

T3

5