Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	751300722	4389759	0	0
wdog_bark_thold_rd_A	751300722	81827	0	0
wdog_bite_thold_rd_A	751300722	71188	0	0
wdog_ctrl_rd_A	751300722	71628	0	0
wdog_regwen_rd_A	751300722	83618	0	0
wkup_ctrl_rd_A	751300722	72388	0	0
wkup_thold_hi_rd_A	751300722	82613	0	0
wkup_thold_lo_rd_A	751300722	72327	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751300722	4389759	0	0
T4	221360	61134	0	0
T5	519448	0	0	0
T6	641508	0	0	0
T7	156412	0	0	0
T8	290684	65866	0	0
T9	45889	0	0	0
T10	282675	74825	0	0
T11	95538	0	0	0
T12	12962	0	0	0
T20	43292	0	0	0
T23	0	26584	0	0
T29	0	130613	0	0
T30	0	139904	0	0
T31	0	67557	0	0
T32	0	56045	0	0
T33	0	148033	0	0
T34	0	69915	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751300722	81827	0	0
T8	290684	6421	0	0
T9	45889	0	0	0
T10	282675	0	0	0
T12	12962	0	0	0
T13	14140	0	0	0
T14	103882	0	0	0
T20	43292	0	0	0
T21	44186	0	0	0
T22	9702	0	0	0
T23	183873	0	0	0
T34	0	7541	0	0
T48	0	6096	0	0
T86	0	6467	0	0
T89	0	4145	0	0
T90	0	2033	0	0
T91	0	3679	0	0
T92	0	4537	0	0
T93	0	6048	0	0
T94	0	1139	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751300722	71188	0	0
T8	290684	5554	0	0
T9	45889	0	0	0
T10	282675	0	0	0
T12	12962	0	0	0
T13	14140	0	0	0
T14	103882	0	0	0
T20	43292	0	0	0
T21	44186	0	0	0
T22	9702	0	0	0
T23	183873	0	0	0
T34	0	6571	0	0
T48	0	5301	0	0
T86	0	5709	0	0
T89	0	3564	0	0
T90	0	1615	0	0
T91	0	3141	0	0
T92	0	3765	0	0
T93	0	5265	0	0
T94	0	1025	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751300722	71628	0	0
T8	290684	5736	0	0
T9	45889	0	0	0
T10	282675	0	0	0
T12	12962	0	0	0
T13	14140	0	0	0
T14	103882	0	0	0
T20	43292	0	0	0
T21	44186	0	0	0
T22	9702	0	0	0
T23	183873	0	0	0
T34	0	6582	0	0
T48	0	5341	0	0
T86	0	5615	0	0
T89	0	3565	0	0
T90	0	1528	0	0
T91	0	3456	0	0
T92	0	3928	0	0
T93	0	5141	0	0
T94	0	915	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751300722	83618	0	0
T8	290684	6377	0	0
T9	45889	0	0	0
T10	282675	0	0	0
T12	12962	0	0	0
T13	14140	0	0	0
T14	103882	0	0	0
T20	43292	0	0	0
T21	44186	0	0	0
T22	9702	0	0	0
T23	183873	0	0	0
T34	0	7459	0	0
T48	0	6395	0	0
T86	0	6544	0	0
T89	0	4450	0	0
T90	0	1711	0	0
T91	0	3751	0	0
T92	0	4273	0	0
T93	0	6203	0	0
T94	0	1228	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751300722	72388	0	0
T8	290684	5574	0	0
T9	45889	0	0	0
T10	282675	0	0	0
T12	12962	0	0	0
T13	14140	0	0	0
T14	103882	0	0	0
T20	43292	0	0	0
T21	44186	0	0	0
T22	9702	0	0	0
T23	183873	0	0	0
T34	0	6110	0	0
T48	0	5487	0	0
T86	0	5716	0	0
T89	0	3871	0	0
T90	0	1717	0	0
T91	0	3230	0	0
T92	0	4072	0	0
T93	0	5158	0	0
T94	0	937	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751300722	82613	0	0
T8	290684	6642	0	0
T9	45889	0	0	0
T10	282675	0	0	0
T12	12962	0	0	0
T13	14140	0	0	0
T14	103882	0	0	0
T20	43292	0	0	0
T21	44186	0	0	0
T22	9702	0	0	0
T23	183873	0	0	0
T34	0	7310	0	0
T48	0	6135	0	0
T86	0	6708	0	0
T89	0	4149	0	0
T90	0	1961	0	0
T91	0	3545	0	0
T92	0	4491	0	0
T93	0	6179	0	0
T94	0	1020	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751300722	72327	0	0
T8	290684	5559	0	0
T9	45889	0	0	0
T10	282675	0	0	0
T12	12962	0	0	0
T13	14140	0	0	0
T14	103882	0	0	0
T20	43292	0	0	0
T21	44186	0	0	0
T22	9702	0	0	0
T23	183873	0	0	0
T34	0	6508	0	0
T48	0	5583	0	0
T86	0	5390	0	0
T89	0	3848	0	0
T90	0	1586	0	0
T91	0	2984	0	0
T92	0	3871	0	0
T93	0	5129	0	0
T94	0	1030	0	0