Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	349484	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4294979	1		T1	213		T2	220		T3	220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1140618	1		T1	61		T2	40		T3	33
values[0x0]	1642812	1		T1	126		T2	140		T3	153
values[0x1]	1861033	1		T1	132		T2	143		T3	143

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156212	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4488251	1		T1	240		T2	245		T3	246

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17426	1		T3	2		T4	707		T5	15
valid_sources[0x01]	17938	1		T3	1		T4	678		T8	765
valid_sources[0x02]	17656	1		T3	1		T4	601		T8	847
valid_sources[0x03]	17925	1		T3	2		T4	482		T8	842
valid_sources[0x04]	16714	1		T3	2		T4	599		T8	740
valid_sources[0x05]	17024	1		T3	5		T4	546		T8	823
valid_sources[0x06]	17850	1		T3	2		T4	613		T8	808
valid_sources[0x07]	18428	1		T4	632		T8	702		T11	1
valid_sources[0x08]	18680	1		T3	1		T4	602		T8	977
valid_sources[0x09]	18008	1		T4	647		T8	906		T11	1
valid_sources[0x0a]	18946	1		T4	587		T8	848		T13	71
valid_sources[0x0b]	18544	1		T3	6		T4	637		T8	688
valid_sources[0x0c]	18182	1		T4	687		T8	843		T11	2
valid_sources[0x0d]	18194	1		T3	1		T4	586		T8	749
valid_sources[0x0e]	19547	1		T3	1		T4	659		T8	855
valid_sources[0x0f]	18546	1		T4	677		T8	791		T11	5
valid_sources[0x10]	19040	1		T3	1		T4	681		T8	824
valid_sources[0x11]	18890	1		T3	1		T4	616		T8	944
valid_sources[0x12]	18064	1		T1	50		T3	2		T4	603
valid_sources[0x13]	17644	1		T4	537		T8	826		T13	115
valid_sources[0x14]	16479	1		T4	590		T8	739		T13	226
valid_sources[0x15]	18502	1		T4	741		T8	802		T11	2
valid_sources[0x16]	18275	1		T3	2		T4	477		T8	700
valid_sources[0x17]	18126	1		T4	638		T8	736		T11	5
valid_sources[0x18]	18321	1		T3	4		T4	601		T8	718
valid_sources[0x19]	17737	1		T3	3		T4	530		T8	741
valid_sources[0x1a]	18783	1		T4	601		T8	906		T11	2
valid_sources[0x1b]	17263	1		T3	1		T4	694		T8	820
valid_sources[0x1c]	17858	1		T4	743		T8	818		T13	316
valid_sources[0x1d]	19329	1		T4	729		T8	780		T11	3
valid_sources[0x1e]	18091	1		T3	2		T4	615		T8	876
valid_sources[0x1f]	18182	1		T3	1		T4	577		T8	861
valid_sources[0x20]	16411	1		T3	2		T4	477		T8	901
valid_sources[0x21]	18432	1		T4	607		T8	830		T13	113
valid_sources[0x22]	17272	1		T4	635		T8	869		T13	21
valid_sources[0x23]	18469	1		T3	5		T4	499		T8	803
valid_sources[0x24]	18905	1		T3	1		T4	664		T8	798
valid_sources[0x25]	18225	1		T4	678		T8	786		T13	744
valid_sources[0x26]	18060	1		T4	590		T8	918		T11	3
valid_sources[0x27]	17904	1		T4	709		T8	770		T11	5
valid_sources[0x28]	18148	1		T3	1		T4	645		T8	847
valid_sources[0x29]	16861	1		T4	632		T8	835		T36	578
valid_sources[0x2a]	18625	1		T4	639		T8	883		T11	1
valid_sources[0x2b]	16844	1		T3	3		T4	603		T8	800
valid_sources[0x2c]	18240	1		T4	624		T8	842		T13	455
valid_sources[0x2d]	16140	1		T3	2		T4	572		T8	792
valid_sources[0x2e]	17821	1		T3	6		T4	689		T8	810
valid_sources[0x2f]	17977	1		T3	2		T4	604		T8	882
valid_sources[0x30]	17905	1		T4	568		T8	850		T36	88
valid_sources[0x31]	20211	1		T4	575		T5	2		T8	796
valid_sources[0x32]	18942	1		T4	607		T8	870		T13	560
valid_sources[0x33]	17283	1		T4	626		T8	916		T13	293
valid_sources[0x34]	19333	1		T3	3		T4	563		T8	914
valid_sources[0x35]	17246	1		T3	2		T4	569		T8	792
valid_sources[0x36]	17748	1		T3	1		T4	730		T8	789
valid_sources[0x37]	18176	1		T3	3		T4	567		T8	847
valid_sources[0x38]	18753	1		T4	713		T8	808		T11	10
valid_sources[0x39]	17070	1		T4	680		T8	896		T13	7
valid_sources[0x3a]	19144	1		T4	641		T8	876		T13	206
valid_sources[0x3b]	16493	1		T4	563		T8	758		T13	325
valid_sources[0x3c]	17868	1		T4	591		T8	932		T13	134
valid_sources[0x3d]	17557	1		T3	2		T4	600		T8	827
valid_sources[0x3e]	16586	1		T1	95		T4	656		T8	903
valid_sources[0x3f]	18086	1		T4	593		T8	861		T13	193
valid_sources[0x40]	18375	1		T3	2		T4	750		T8	974
valid_sources[0x41]	19579	1		T3	1		T4	725		T6	22
valid_sources[0x42]	18139	1		T4	614		T8	860		T13	46
valid_sources[0x43]	18652	1		T4	608		T8	791		T11	5
valid_sources[0x44]	17915	1		T3	1		T4	785		T8	731
valid_sources[0x45]	17461	1		T4	686		T8	888		T13	66
valid_sources[0x46]	17317	1		T3	2		T4	652		T8	772
valid_sources[0x47]	16246	1		T4	519		T8	811		T13	258
valid_sources[0x48]	18068	1		T4	539		T8	819		T11	1
valid_sources[0x49]	18031	1		T3	2		T4	723		T8	907
valid_sources[0x4a]	17060	1		T4	534		T8	795		T11	3
valid_sources[0x4b]	19688	1		T1	75		T3	1		T4	538
valid_sources[0x4c]	18912	1		T4	704		T8	745		T36	240
valid_sources[0x4d]	18526	1		T3	2		T4	684		T8	906
valid_sources[0x4e]	18154	1		T3	5		T4	592		T8	802
valid_sources[0x4f]	19182	1		T4	654		T8	763		T11	3
valid_sources[0x50]	18843	1		T4	726		T8	804		T13	86
valid_sources[0x51]	18494	1		T4	613		T8	878		T11	8
valid_sources[0x52]	18575	1		T4	542		T8	779		T13	407
valid_sources[0x53]	16957	1		T4	692		T8	787		T11	4
valid_sources[0x54]	17856	1		T4	527		T8	783		T13	469
valid_sources[0x55]	19386	1		T3	1		T4	528		T8	827
valid_sources[0x56]	17921	1		T3	2		T4	643		T8	910
valid_sources[0x57]	18519	1		T4	752		T8	801		T11	1
valid_sources[0x58]	19149	1		T4	707		T8	815		T11	1
valid_sources[0x59]	18204	1		T3	2		T4	634		T8	847
valid_sources[0x5a]	19647	1		T3	4		T4	636		T8	752
valid_sources[0x5b]	19117	1		T3	2		T4	567		T8	912
valid_sources[0x5c]	18125	1		T3	3		T4	686		T8	865
valid_sources[0x5d]	17813	1		T4	540		T8	738		T13	239
valid_sources[0x5e]	18137	1		T3	1		T4	754		T8	834
valid_sources[0x5f]	18203	1		T3	1		T4	555		T8	823
valid_sources[0x60]	17611	1		T3	2		T4	654		T8	817
valid_sources[0x61]	19853	1		T1	7		T3	2		T4	615
valid_sources[0x62]	16987	1		T4	612		T8	827		T11	4
valid_sources[0x63]	18166	1		T1	6		T4	659		T8	999
valid_sources[0x64]	18192	1		T3	1		T4	675		T8	852
valid_sources[0x65]	18074	1		T3	2		T4	625		T8	824
valid_sources[0x66]	18518	1		T3	1		T4	745		T8	776
valid_sources[0x67]	18464	1		T3	3		T4	560		T8	793
valid_sources[0x68]	18979	1		T3	2		T4	455		T8	788
valid_sources[0x69]	19437	1		T4	734		T8	828		T13	379
valid_sources[0x6a]	18776	1		T3	1		T4	565		T8	893
valid_sources[0x6b]	18709	1		T3	1		T4	701		T8	752
valid_sources[0x6c]	17610	1		T3	2		T4	619		T8	742
valid_sources[0x6d]	17940	1		T4	602		T8	807		T13	357
valid_sources[0x6e]	17960	1		T3	1		T4	697		T8	824
valid_sources[0x6f]	18289	1		T3	1		T4	654		T8	847
valid_sources[0x70]	17959	1		T4	685		T8	906		T11	1
valid_sources[0x71]	15869	1		T3	2		T4	591		T8	782
valid_sources[0x72]	18613	1		T3	3		T4	704		T8	798
valid_sources[0x73]	18388	1		T3	1		T4	505		T8	856
valid_sources[0x74]	19990	1		T3	1		T4	647		T8	804
valid_sources[0x75]	17604	1		T3	4		T4	572		T8	735
valid_sources[0x76]	18288	1		T3	2		T4	690		T8	824
valid_sources[0x77]	18718	1		T4	543		T8	657		T13	2
valid_sources[0x78]	18627	1		T3	2		T4	698		T8	719
valid_sources[0x79]	17296	1		T3	1		T4	638		T8	773
valid_sources[0x7a]	17721	1		T1	69		T3	1		T4	630
valid_sources[0x7b]	18434	1		T4	569		T8	774		T11	2
valid_sources[0x7c]	19331	1		T3	1		T4	590		T8	772
valid_sources[0x7d]	19655	1		T4	643		T8	834		T13	457
valid_sources[0x7e]	18339	1		T3	3		T4	701		T8	819
valid_sources[0x7f]	19207	1		T3	2		T4	624		T8	833
valid_sources[0x80]	18148	1		T3	2		T4	523		T8	859

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1069473

1

T1

34

T2

21

T3

16

values[0x0]

all_enables

biggest_size

1612795

1

T1

94

T2

97

T3

110

values[0x1]

all_enables

biggest_size

1612711

1

T1

85

T2

102

T3

94