Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	747104463	5080459	0	0
wdog_bark_thold_rd_A	747104463	105596	0	0
wdog_bite_thold_rd_A	747104463	93549	0	0
wdog_ctrl_rd_A	747104463	94069	0	0
wdog_regwen_rd_A	747104463	107401	0	0
wkup_ctrl_rd_A	747104463	94287	0	0
wkup_thold_hi_rd_A	747104463	107423	0	0
wkup_thold_lo_rd_A	747104463	93119	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747104463	5080459	0	0
T4	473177	179227	0	0
T5	52279	0	0	0
T6	53399	0	0	0
T7	14723	0	0	0
T8	898689	249746	0	0
T9	618665	0	0	0
T10	958040	0	0	0
T11	655193	0	0	0
T12	4735	0	0	0
T13	253534	70550	0	0
T24	0	92820	0	0
T27	0	120060	0	0
T36	0	78963	0	0
T37	0	128124	0	0
T38	0	46094	0	0
T39	0	176253	0	0
T40	0	260407	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747104463	105596	0	0
T36	413413	7283	0	0
T37	345990	0	0	0
T38	0	2309	0	0
T41	976164	0	0	0
T42	320620	0	0	0
T43	266389	0	0	0
T85	0	3082	0	0
T86	0	17547	0	0
T89	0	5901	0	0
T91	0	7198	0	0
T92	0	7866	0	0
T93	0	2767	0	0
T94	0	11462	0	0
T95	0	6308	0	0
T96	44420	0	0	0
T97	4829	0	0	0
T98	57635	0	0	0
T99	10434	0	0	0
T100	539031	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747104463	93549	0	0
T36	413413	6773	0	0
T37	345990	0	0	0
T38	0	2198	0	0
T41	976164	0	0	0
T42	320620	0	0	0
T43	266389	0	0	0
T85	0	2632	0	0
T86	0	15183	0	0
T89	0	5373	0	0
T91	0	5939	0	0
T92	0	6684	0	0
T93	0	2449	0	0
T94	0	10247	0	0
T95	0	5414	0	0
T96	44420	0	0	0
T97	4829	0	0	0
T98	57635	0	0	0
T99	10434	0	0	0
T100	539031	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747104463	94069	0	0
T36	413413	7047	0	0
T37	345990	0	0	0
T38	0	2096	0	0
T41	976164	0	0	0
T42	320620	0	0	0
T43	266389	0	0	0
T85	0	2813	0	0
T86	0	15725	0	0
T89	0	4947	0	0
T91	0	6146	0	0
T92	0	6490	0	0
T93	0	2577	0	0
T94	0	10193	0	0
T95	0	5417	0	0
T96	44420	0	0	0
T97	4829	0	0	0
T98	57635	0	0	0
T99	10434	0	0	0
T100	539031	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747104463	107401	0	0
T36	413413	7788	0	0
T37	345990	0	0	0
T38	0	2527	0	0
T41	976164	0	0	0
T42	320620	0	0	0
T43	266389	0	0	0
T85	0	3153	0	0
T86	0	18104	0	0
T89	0	5645	0	0
T91	0	6800	0	0
T92	0	7771	0	0
T93	0	3040	0	0
T94	0	11973	0	0
T95	0	6068	0	0
T96	44420	0	0	0
T97	4829	0	0	0
T98	57635	0	0	0
T99	10434	0	0	0
T100	539031	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747104463	94287	0	0
T36	413413	6952	0	0
T37	345990	0	0	0
T38	0	2157	0	0
T41	976164	0	0	0
T42	320620	0	0	0
T43	266389	0	0	0
T85	0	2615	0	0
T86	0	15979	0	0
T89	0	5144	0	0
T91	0	6081	0	0
T92	0	6637	0	0
T93	0	2671	0	0
T94	0	10445	0	0
T95	0	5373	0	0
T96	44420	0	0	0
T97	4829	0	0	0
T98	57635	0	0	0
T99	10434	0	0	0
T100	539031	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747104463	107423	0	0
T36	413413	8078	0	0
T37	345990	0	0	0
T38	0	2842	0	0
T41	976164	0	0	0
T42	320620	0	0	0
T43	266389	0	0	0
T85	0	2961	0	0
T86	0	18689	0	0
T89	0	5852	0	0
T91	0	6850	0	0
T92	0	6973	0	0
T93	0	3155	0	0
T94	0	11459	0	0
T95	0	6220	0	0
T96	44420	0	0	0
T97	4829	0	0	0
T98	57635	0	0	0
T99	10434	0	0	0
T100	539031	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747104463	93119	0	0
T36	413413	6672	0	0
T37	345990	0	0	0
T38	0	2031	0	0
T41	976164	0	0	0
T42	320620	0	0	0
T43	266389	0	0	0
T85	0	2811	0	0
T86	0	15961	0	0
T89	0	5084	0	0
T91	0	6087	0	0
T92	0	6674	0	0
T93	0	2484	0	0
T94	0	9809	0	0
T95	0	5584	0	0
T96	44420	0	0	0
T97	4829	0	0	0
T98	57635	0	0	0
T99	10434	0	0	0
T100	539031	0	0	0