Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	270571	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3293578	1		T1	98104		T2	18		T3	220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	877742	1		T1	25882		T2	1		T3	24
values[0x0]	1260888	1		T1	37601		T2	12		T3	155
values[0x1]	1425519	1		T1	42190		T2	9		T3	136

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122383	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3441766	1		T1	102385		T2	18		T3	235

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13200	1		T1	335		T2	1		T3	1
valid_sources[0x01]	15196	1		T1	641		T3	3		T7	1
valid_sources[0x02]	13573	1		T1	458		T8	2		T10	149
valid_sources[0x03]	14482	1		T1	452		T7	1		T8	1
valid_sources[0x04]	14334	1		T1	253		T2	1		T10	356
valid_sources[0x05]	14233	1		T1	43		T3	5		T4	1
valid_sources[0x06]	13496	1		T1	465		T8	2		T9	1
valid_sources[0x07]	14203	1		T1	300		T3	3		T7	1
valid_sources[0x08]	14259	1		T1	672		T3	1		T8	1
valid_sources[0x09]	14110	1		T1	400		T3	2		T8	1
valid_sources[0x0a]	13203	1		T1	148		T3	2		T7	1
valid_sources[0x0b]	13989	1		T1	296		T3	6		T8	1
valid_sources[0x0c]	14959	1		T1	221		T3	3		T10	184
valid_sources[0x0d]	13452	1		T1	321		T3	3		T4	5
valid_sources[0x0e]	14937	1		T1	457		T8	13		T10	124
valid_sources[0x0f]	13126	1		T1	181		T3	3		T10	82
valid_sources[0x10]	14554	1		T1	421		T8	2		T9	1
valid_sources[0x11]	13510	1		T1	307		T3	1		T10	258
valid_sources[0x12]	13417	1		T1	295		T3	1		T10	557
valid_sources[0x13]	13907	1		T1	490		T3	1		T10	261
valid_sources[0x14]	13178	1		T1	45		T2	1		T3	1
valid_sources[0x15]	14828	1		T1	188		T3	2		T8	1
valid_sources[0x16]	13753	1		T1	393		T10	221		T11	3
valid_sources[0x17]	13348	1		T1	546		T3	4		T7	1
valid_sources[0x18]	13332	1		T1	137		T3	5		T10	327
valid_sources[0x19]	13885	1		T1	715		T2	1		T10	186
valid_sources[0x1a]	14334	1		T1	557		T3	1		T8	5
valid_sources[0x1b]	13851	1		T1	120		T3	1		T8	1
valid_sources[0x1c]	14194	1		T1	446		T10	14		T12	207
valid_sources[0x1d]	13807	1		T1	669		T7	2		T10	278
valid_sources[0x1e]	13726	1		T1	708		T3	3		T8	1
valid_sources[0x1f]	14078	1		T1	677		T3	2		T8	13
valid_sources[0x20]	13235	1		T1	107		T3	3		T8	2
valid_sources[0x21]	14431	1		T1	489		T5	20		T10	141
valid_sources[0x22]	13606	1		T1	661		T3	1		T10	17
valid_sources[0x23]	14383	1		T1	561		T10	174		T12	222
valid_sources[0x24]	14014	1		T1	207		T3	1		T8	1
valid_sources[0x25]	14286	1		T1	298		T8	3		T10	753
valid_sources[0x26]	14024	1		T1	451		T3	2		T8	3
valid_sources[0x27]	13982	1		T1	974		T3	1		T8	2
valid_sources[0x28]	14218	1		T1	156		T3	1		T8	1
valid_sources[0x29]	14056	1		T1	38		T3	2		T10	30
valid_sources[0x2a]	14257	1		T1	1220		T3	1		T10	315
valid_sources[0x2b]	14076	1		T1	233		T8	1		T10	214
valid_sources[0x2c]	12868	1		T1	255		T3	1		T10	137
valid_sources[0x2d]	14650	1		T1	660		T3	1		T4	5
valid_sources[0x2e]	14323	1		T1	347		T8	2		T10	260
valid_sources[0x2f]	12919	1		T1	212		T10	224		T12	214
valid_sources[0x30]	13727	1		T1	244		T3	1		T8	1
valid_sources[0x31]	14019	1		T1	639		T3	1		T8	4
valid_sources[0x32]	13542	1		T1	158		T2	1		T3	2
valid_sources[0x33]	14093	1		T1	144		T3	1		T8	2
valid_sources[0x34]	14289	1		T1	279		T2	1		T3	2
valid_sources[0x35]	14899	1		T1	842		T3	1		T10	541
valid_sources[0x36]	14021	1		T1	431		T3	2		T10	427
valid_sources[0x37]	13320	1		T1	287		T3	1		T10	20
valid_sources[0x38]	13811	1		T1	287		T3	2		T7	1
valid_sources[0x39]	15266	1		T1	825		T3	1		T8	1
valid_sources[0x3a]	15137	1		T1	386		T10	137		T11	1
valid_sources[0x3b]	13710	1		T1	297		T10	361		T11	2
valid_sources[0x3c]	14385	1		T1	688		T10	321		T11	3
valid_sources[0x3d]	14115	1		T1	478		T3	1		T8	5
valid_sources[0x3e]	13806	1		T1	270		T2	1		T3	4
valid_sources[0x3f]	14102	1		T1	255		T3	5		T10	163
valid_sources[0x40]	14612	1		T1	799		T3	2		T10	61
valid_sources[0x41]	13715	1		T1	149		T10	348		T12	200
valid_sources[0x42]	13667	1		T1	261		T8	5		T10	36
valid_sources[0x43]	13665	1		T1	126		T3	3		T10	227
valid_sources[0x44]	13638	1		T1	344		T3	1		T10	311
valid_sources[0x45]	13619	1		T1	273		T3	2		T10	306
valid_sources[0x46]	15086	1		T1	640		T3	2		T8	1
valid_sources[0x47]	13936	1		T1	1113		T3	5		T10	279
valid_sources[0x48]	13541	1		T1	226		T10	133		T12	197
valid_sources[0x49]	13703	1		T1	309		T3	2		T8	4
valid_sources[0x4a]	15159	1		T1	496		T3	3		T10	313
valid_sources[0x4b]	13369	1		T1	332		T8	1		T10	358
valid_sources[0x4c]	13989	1		T1	175		T3	4		T10	210
valid_sources[0x4d]	13037	1		T1	333		T3	1		T8	3
valid_sources[0x4e]	13760	1		T1	143		T3	1		T8	1
valid_sources[0x4f]	14087	1		T1	777		T3	1		T8	2
valid_sources[0x50]	13633	1		T1	696		T2	1		T10	36
valid_sources[0x51]	14332	1		T1	348		T10	263		T11	3
valid_sources[0x52]	13223	1		T1	98		T8	1		T10	22
valid_sources[0x53]	13319	1		T1	298		T8	10		T10	34
valid_sources[0x54]	14890	1		T1	972		T7	2		T8	1
valid_sources[0x55]	14237	1		T1	177		T3	2		T8	3
valid_sources[0x56]	13863	1		T1	685		T7	1		T10	77
valid_sources[0x57]	13761	1		T1	585		T3	1		T8	9
valid_sources[0x58]	13514	1		T1	451		T9	1		T10	116
valid_sources[0x59]	14726	1		T1	587		T3	2		T10	146
valid_sources[0x5a]	14005	1		T1	826		T8	1		T10	114
valid_sources[0x5b]	13117	1		T1	147		T3	1		T7	2
valid_sources[0x5c]	14219	1		T1	141		T10	566		T11	3
valid_sources[0x5d]	13312	1		T1	246		T3	1		T8	2
valid_sources[0x5e]	13942	1		T1	333		T3	2		T10	224
valid_sources[0x5f]	13684	1		T1	314		T3	1		T8	6
valid_sources[0x60]	14010	1		T1	793		T10	475		T12	237
valid_sources[0x61]	13916	1		T1	269		T3	1		T10	93
valid_sources[0x62]	13738	1		T1	796		T8	1		T10	148
valid_sources[0x63]	13488	1		T1	342		T3	1		T8	1
valid_sources[0x64]	13315	1		T1	832		T2	1		T3	3
valid_sources[0x65]	13625	1		T1	111		T2	2		T3	3
valid_sources[0x66]	14584	1		T1	109		T3	5		T8	3
valid_sources[0x67]	13489	1		T1	161		T8	2		T10	277
valid_sources[0x68]	13759	1		T1	642		T10	5		T12	224
valid_sources[0x69]	13787	1		T1	421		T10	395		T11	2
valid_sources[0x6a]	14759	1		T1	710		T3	1		T8	5
valid_sources[0x6b]	13995	1		T1	1277		T3	1		T4	2
valid_sources[0x6c]	13764	1		T1	537		T3	1		T10	224
valid_sources[0x6d]	13616	1		T1	728		T4	1		T10	195
valid_sources[0x6e]	13890	1		T1	644		T3	2		T8	6
valid_sources[0x6f]	13758	1		T1	121		T3	4		T10	97
valid_sources[0x70]	13327	1		T1	194		T8	5		T10	22
valid_sources[0x71]	14331	1		T1	784		T7	3		T10	86
valid_sources[0x72]	14526	1		T1	464		T3	2		T4	3
valid_sources[0x73]	13589	1		T1	182		T2	1		T10	411
valid_sources[0x74]	13246	1		T1	602		T3	1		T10	374
valid_sources[0x75]	14969	1		T1	532		T10	445		T12	201
valid_sources[0x76]	14769	1		T1	451		T10	242		T12	198
valid_sources[0x77]	12750	1		T1	440		T3	2		T10	20
valid_sources[0x78]	13114	1		T1	462		T2	1		T10	110
valid_sources[0x79]	14237	1		T1	738		T9	2		T10	303
valid_sources[0x7a]	12970	1		T1	52		T3	1		T10	342
valid_sources[0x7b]	13783	1		T1	497		T10	277		T11	2
valid_sources[0x7c]	14037	1		T1	376		T8	1		T10	305
valid_sources[0x7d]	13273	1		T1	329		T10	318		T11	3
valid_sources[0x7e]	13527	1		T1	456		T8	6		T10	11
valid_sources[0x7f]	13254	1		T1	316		T3	2		T10	219
valid_sources[0x80]	13648	1		T1	436		T10	515		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

821396

1

T1

24410

T2

1

T3

14

values[0x0]

all_enables

biggest_size

1237011

1

T1

36949

T2

11

T3

109

values[0x1]

all_enables

biggest_size

1235171

1

T1

36745

T2

6

T3

97