Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	774413309	3873356	0	0
wdog_bark_thold_rd_A	774413309	108340	0	0
wdog_bite_thold_rd_A	774413309	95446	0	0
wdog_ctrl_rd_A	774413309	95375	0	0
wdog_regwen_rd_A	774413309	108770	0	0
wkup_ctrl_rd_A	774413309	94492	0	0
wkup_thold_hi_rd_A	774413309	108286	0	0
wkup_thold_lo_rd_A	774413309	95277	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774413309	3873356	0	0
T1	496092	112401	0	0
T2	57412	0	0	0
T3	562102	0	0	0
T4	611441	0	0	0
T5	481353	0	0	0
T6	291182	0	0	0
T7	11901	0	0	0
T8	110284	0	0	0
T9	120023	0	0	0
T10	258340	61058	0	0
T12	0	55742	0	0
T28	0	221244	0	0
T30	0	294451	0	0
T31	0	119289	0	0
T39	0	50040	0	0
T40	0	33317	0	0
T41	0	100698	0	0
T42	0	84666	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774413309	108340	0	0
T1	496092	11296	0	0
T2	57412	0	0	0
T3	562102	0	0	0
T4	611441	0	0	0
T5	481353	0	0	0
T6	291182	0	0	0
T7	11901	0	0	0
T8	110284	0	0	0
T9	120023	0	0	0
T10	258340	6067	0	0
T40	0	3187	0	0
T42	0	8156	0	0
T55	0	12274	0	0
T98	0	8471	0	0
T99	0	4519	0	0
T100	0	702	0	0
T101	0	8271	0	0
T102	0	10612	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774413309	95446	0	0
T1	496092	10310	0	0
T2	57412	0	0	0
T3	562102	0	0	0
T4	611441	0	0	0
T5	481353	0	0	0
T6	291182	0	0	0
T7	11901	0	0	0
T8	110284	0	0	0
T9	120023	0	0	0
T10	258340	5309	0	0
T40	0	2639	0	0
T42	0	6792	0	0
T55	0	10712	0	0
T98	0	7123	0	0
T99	0	3944	0	0
T100	0	715	0	0
T101	0	7558	0	0
T102	0	9571	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774413309	95375	0	0
T1	496092	9712	0	0
T2	57412	0	0	0
T3	562102	0	0	0
T4	611441	0	0	0
T5	481353	0	0	0
T6	291182	0	0	0
T7	11901	0	0	0
T8	110284	0	0	0
T9	120023	0	0	0
T10	258340	5214	0	0
T40	0	2911	0	0
T42	0	7202	0	0
T55	0	11032	0	0
T98	0	7305	0	0
T99	0	3830	0	0
T100	0	706	0	0
T101	0	7686	0	0
T102	0	9236	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774413309	108770	0	0
T1	496092	11259	0	0
T2	57412	0	0	0
T3	562102	0	0	0
T4	611441	0	0	0
T5	481353	0	0	0
T6	291182	0	0	0
T7	11901	0	0	0
T8	110284	0	0	0
T9	120023	0	0	0
T10	258340	5708	0	0
T40	0	3196	0	0
T42	0	8165	0	0
T55	0	12764	0	0
T98	0	8302	0	0
T99	0	4488	0	0
T100	0	762	0	0
T101	0	8725	0	0
T102	0	10843	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774413309	94492	0	0
T1	496092	10135	0	0
T2	57412	0	0	0
T3	562102	0	0	0
T4	611441	0	0	0
T5	481353	0	0	0
T6	291182	0	0	0
T7	11901	0	0	0
T8	110284	0	0	0
T9	120023	0	0	0
T10	258340	5369	0	0
T40	0	2619	0	0
T42	0	7314	0	0
T55	0	10360	0	0
T98	0	6976	0	0
T99	0	4045	0	0
T100	0	701	0	0
T101	0	7598	0	0
T102	0	9452	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774413309	108286	0	0
T1	496092	11861	0	0
T2	57412	0	0	0
T3	562102	0	0	0
T4	611441	0	0	0
T5	481353	0	0	0
T6	291182	0	0	0
T7	11901	0	0	0
T8	110284	0	0	0
T9	120023	0	0	0
T10	258340	6031	0	0
T40	0	3085	0	0
T42	0	8221	0	0
T55	0	11985	0	0
T98	0	7965	0	0
T99	0	4388	0	0
T100	0	791	0	0
T101	0	8805	0	0
T102	0	10822	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774413309	95277	0	0
T1	496092	10165	0	0
T2	57412	0	0	0
T3	562102	0	0	0
T4	611441	0	0	0
T5	481353	0	0	0
T6	291182	0	0	0
T7	11901	0	0	0
T8	110284	0	0	0
T9	120023	0	0	0
T10	258340	5046	0	0
T40	0	2757	0	0
T42	0	6961	0	0
T55	0	11077	0	0
T98	0	6998	0	0
T99	0	4071	0	0
T100	0	613	0	0
T101	0	7861	0	0
T102	0	9482	0	0