Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 16 | 15 | 93.75 |
Logical | 16 | 15 | 93.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T32,T33,T34 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T10,T13 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
38324809 |
0 |
0 |
T1 |
4960920 |
345789 |
0 |
0 |
T2 |
574120 |
33404 |
0 |
0 |
T3 |
5621020 |
99111 |
0 |
0 |
T4 |
6114410 |
5465 |
0 |
0 |
T5 |
4813530 |
6742 |
0 |
0 |
T6 |
2911820 |
31565 |
0 |
0 |
T7 |
119010 |
8084 |
0 |
0 |
T8 |
1102840 |
114933 |
0 |
0 |
T9 |
1200230 |
19049 |
0 |
0 |
T10 |
2583400 |
158937 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34511070 |
33577430 |
0 |
0 |
T1 |
413400 |
412170 |
0 |
0 |
T2 |
1180 |
200 |
0 |
0 |
T3 |
468400 |
461330 |
0 |
0 |
T4 |
48900 |
48060 |
0 |
0 |
T5 |
35640 |
35130 |
0 |
0 |
T6 |
58810 |
58240 |
0 |
0 |
T7 |
1120 |
210 |
0 |
0 |
T8 |
919030 |
911680 |
0 |
0 |
T9 |
33800 |
33270 |
0 |
0 |
T10 |
156560 |
155290 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
42038 |
0 |
0 |
T1 |
4960920 |
904 |
0 |
0 |
T2 |
574120 |
18 |
0 |
0 |
T3 |
5621020 |
234 |
0 |
0 |
T4 |
6114410 |
16 |
0 |
0 |
T5 |
4813530 |
16 |
0 |
0 |
T6 |
2911820 |
16 |
0 |
0 |
T7 |
119010 |
18 |
0 |
0 |
T8 |
1102840 |
284 |
0 |
0 |
T9 |
1200230 |
16 |
0 |
0 |
T10 |
2583400 |
281 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4960920 |
4953520 |
0 |
0 |
T2 |
574120 |
573410 |
0 |
0 |
T3 |
5621020 |
5620270 |
0 |
0 |
T4 |
6114410 |
6113900 |
0 |
0 |
T5 |
4813530 |
4812990 |
0 |
0 |
T6 |
2911820 |
2911740 |
0 |
0 |
T7 |
119010 |
118100 |
0 |
0 |
T8 |
1102840 |
1102770 |
0 |
0 |
T9 |
1200230 |
1200150 |
0 |
0 |
T10 |
2583400 |
2577230 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
4849400 |
0 |
0 |
T1 |
496092 |
48647 |
0 |
0 |
T2 |
57412 |
5649 |
0 |
0 |
T3 |
562102 |
14589 |
0 |
0 |
T4 |
611441 |
683 |
0 |
0 |
T5 |
481353 |
872 |
0 |
0 |
T6 |
291182 |
3946 |
0 |
0 |
T7 |
11901 |
1265 |
0 |
0 |
T8 |
110284 |
16915 |
0 |
0 |
T9 |
120023 |
2470 |
0 |
0 |
T10 |
258340 |
22510 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
5443 |
0 |
0 |
T1 |
496092 |
128 |
0 |
0 |
T2 |
57412 |
3 |
0 |
0 |
T3 |
562102 |
35 |
0 |
0 |
T4 |
611441 |
2 |
0 |
0 |
T5 |
481353 |
2 |
0 |
0 |
T6 |
291182 |
2 |
0 |
0 |
T7 |
11901 |
3 |
0 |
0 |
T8 |
110284 |
41 |
0 |
0 |
T9 |
120023 |
2 |
0 |
0 |
T10 |
258340 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
5200076 |
0 |
0 |
T1 |
496092 |
52893 |
0 |
0 |
T2 |
57412 |
3325 |
0 |
0 |
T3 |
562102 |
13242 |
0 |
0 |
T4 |
611441 |
1034 |
0 |
0 |
T5 |
481353 |
1391 |
0 |
0 |
T6 |
291182 |
5920 |
0 |
0 |
T7 |
11901 |
829 |
0 |
0 |
T8 |
110284 |
16798 |
0 |
0 |
T9 |
120023 |
3885 |
0 |
0 |
T10 |
258340 |
22944 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
5890 |
0 |
0 |
T1 |
496092 |
136 |
0 |
0 |
T2 |
57412 |
2 |
0 |
0 |
T3 |
562102 |
33 |
0 |
0 |
T4 |
611441 |
3 |
0 |
0 |
T5 |
481353 |
3 |
0 |
0 |
T6 |
291182 |
3 |
0 |
0 |
T7 |
11901 |
2 |
0 |
0 |
T8 |
110284 |
42 |
0 |
0 |
T9 |
120023 |
3 |
0 |
0 |
T10 |
258340 |
41 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
2850240 |
0 |
0 |
T1 |
496092 |
21294 |
0 |
0 |
T2 |
57412 |
1873 |
0 |
0 |
T3 |
562102 |
5328 |
0 |
0 |
T4 |
611441 |
334 |
0 |
0 |
T5 |
481353 |
368 |
0 |
0 |
T6 |
291182 |
1971 |
0 |
0 |
T7 |
11901 |
354 |
0 |
0 |
T8 |
110284 |
6502 |
0 |
0 |
T9 |
120023 |
1055 |
0 |
0 |
T10 |
258340 |
10658 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
3182 |
0 |
0 |
T1 |
496092 |
60 |
0 |
0 |
T2 |
57412 |
1 |
0 |
0 |
T3 |
562102 |
14 |
0 |
0 |
T4 |
611441 |
1 |
0 |
0 |
T5 |
481353 |
1 |
0 |
0 |
T6 |
291182 |
1 |
0 |
0 |
T7 |
11901 |
1 |
0 |
0 |
T8 |
110284 |
18 |
0 |
0 |
T9 |
120023 |
1 |
0 |
0 |
T10 |
258340 |
19 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
2829833 |
0 |
0 |
T1 |
496092 |
21385 |
0 |
0 |
T2 |
57412 |
1879 |
0 |
0 |
T3 |
562102 |
5356 |
0 |
0 |
T4 |
611441 |
338 |
0 |
0 |
T5 |
481353 |
370 |
0 |
0 |
T6 |
291182 |
1973 |
0 |
0 |
T7 |
11901 |
360 |
0 |
0 |
T8 |
110284 |
6515 |
0 |
0 |
T9 |
120023 |
1057 |
0 |
0 |
T10 |
258340 |
10339 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
3175 |
0 |
0 |
T1 |
496092 |
60 |
0 |
0 |
T2 |
57412 |
1 |
0 |
0 |
T3 |
562102 |
14 |
0 |
0 |
T4 |
611441 |
1 |
0 |
0 |
T5 |
481353 |
1 |
0 |
0 |
T6 |
291182 |
1 |
0 |
0 |
T7 |
11901 |
1 |
0 |
0 |
T8 |
110284 |
18 |
0 |
0 |
T9 |
120023 |
1 |
0 |
0 |
T10 |
258340 |
19 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
4209171 |
0 |
0 |
T1 |
496092 |
36318 |
0 |
0 |
T2 |
57412 |
3324 |
0 |
0 |
T3 |
562102 |
10609 |
0 |
0 |
T4 |
611441 |
720 |
0 |
0 |
T5 |
481353 |
907 |
0 |
0 |
T6 |
291182 |
3953 |
0 |
0 |
T7 |
11901 |
824 |
0 |
0 |
T8 |
110284 |
11672 |
0 |
0 |
T9 |
120023 |
2478 |
0 |
0 |
T10 |
258340 |
16528 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
4604 |
0 |
0 |
T1 |
496092 |
92 |
0 |
0 |
T2 |
57412 |
2 |
0 |
0 |
T3 |
562102 |
26 |
0 |
0 |
T4 |
611441 |
2 |
0 |
0 |
T5 |
481353 |
2 |
0 |
0 |
T6 |
291182 |
2 |
0 |
0 |
T7 |
11901 |
2 |
0 |
0 |
T8 |
110284 |
29 |
0 |
0 |
T9 |
120023 |
2 |
0 |
0 |
T10 |
258340 |
29 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
2805582 |
0 |
0 |
T1 |
496092 |
21364 |
0 |
0 |
T2 |
57412 |
1859 |
0 |
0 |
T3 |
562102 |
5300 |
0 |
0 |
T4 |
611441 |
325 |
0 |
0 |
T5 |
481353 |
364 |
0 |
0 |
T6 |
291182 |
1969 |
0 |
0 |
T7 |
11901 |
347 |
0 |
0 |
T8 |
110284 |
6612 |
0 |
0 |
T9 |
120023 |
1053 |
0 |
0 |
T10 |
258340 |
10627 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
3163 |
0 |
0 |
T1 |
496092 |
60 |
0 |
0 |
T2 |
57412 |
1 |
0 |
0 |
T3 |
562102 |
14 |
0 |
0 |
T4 |
611441 |
1 |
0 |
0 |
T5 |
481353 |
1 |
0 |
0 |
T6 |
291182 |
1 |
0 |
0 |
T7 |
11901 |
1 |
0 |
0 |
T8 |
110284 |
18 |
0 |
0 |
T9 |
120023 |
1 |
0 |
0 |
T10 |
258340 |
19 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
2830597 |
0 |
0 |
T1 |
496092 |
21622 |
0 |
0 |
T2 |
57412 |
1842 |
0 |
0 |
T3 |
562102 |
5272 |
0 |
0 |
T4 |
611441 |
318 |
0 |
0 |
T5 |
481353 |
352 |
0 |
0 |
T6 |
291182 |
1967 |
0 |
0 |
T7 |
11901 |
341 |
0 |
0 |
T8 |
110284 |
6496 |
0 |
0 |
T9 |
120023 |
1051 |
0 |
0 |
T10 |
258340 |
10714 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
3165 |
0 |
0 |
T1 |
496092 |
60 |
0 |
0 |
T2 |
57412 |
1 |
0 |
0 |
T3 |
562102 |
14 |
0 |
0 |
T4 |
611441 |
1 |
0 |
0 |
T5 |
481353 |
1 |
0 |
0 |
T6 |
291182 |
1 |
0 |
0 |
T7 |
11901 |
1 |
0 |
0 |
T8 |
110284 |
18 |
0 |
0 |
T9 |
120023 |
1 |
0 |
0 |
T10 |
258340 |
19 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
5309129 |
0 |
0 |
T1 |
496092 |
52866 |
0 |
0 |
T2 |
57412 |
6159 |
0 |
0 |
T3 |
562102 |
17417 |
0 |
0 |
T4 |
611441 |
698 |
0 |
0 |
T5 |
481353 |
888 |
0 |
0 |
T6 |
291182 |
3949 |
0 |
0 |
T7 |
11901 |
1716 |
0 |
0 |
T8 |
110284 |
18641 |
0 |
0 |
T9 |
120023 |
2474 |
0 |
0 |
T10 |
258340 |
23213 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
5404 |
0 |
0 |
T1 |
496092 |
128 |
0 |
0 |
T2 |
57412 |
3 |
0 |
0 |
T3 |
562102 |
35 |
0 |
0 |
T4 |
611441 |
2 |
0 |
0 |
T5 |
481353 |
2 |
0 |
0 |
T6 |
291182 |
2 |
0 |
0 |
T7 |
11901 |
3 |
0 |
0 |
T8 |
110284 |
41 |
0 |
0 |
T9 |
120023 |
2 |
0 |
0 |
T10 |
258340 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T12 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T7,T8 |
1 | 1 | Covered | T1,T11,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
5003100 |
0 |
0 |
T1 |
496092 |
48439 |
0 |
0 |
T2 |
57412 |
5616 |
0 |
0 |
T3 |
562102 |
15598 |
0 |
0 |
T4 |
611441 |
667 |
0 |
0 |
T5 |
481353 |
855 |
0 |
0 |
T6 |
291182 |
3942 |
0 |
0 |
T7 |
11901 |
1653 |
0 |
0 |
T8 |
110284 |
17336 |
0 |
0 |
T9 |
120023 |
2466 |
0 |
0 |
T10 |
258340 |
22363 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
5459 |
0 |
0 |
T1 |
496092 |
128 |
0 |
0 |
T2 |
57412 |
3 |
0 |
0 |
T3 |
562102 |
35 |
0 |
0 |
T4 |
611441 |
2 |
0 |
0 |
T5 |
481353 |
2 |
0 |
0 |
T6 |
291182 |
2 |
0 |
0 |
T7 |
11901 |
3 |
0 |
0 |
T8 |
110284 |
41 |
0 |
0 |
T9 |
120023 |
2 |
0 |
0 |
T10 |
258340 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
| Total | Covered | Percent |
Conditions | 16 | 15 | 93.75 |
Logical | 16 | 15 | 93.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T32,T33,T34 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T10,T13 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
2437681 |
0 |
0 |
T1 |
496092 |
20961 |
0 |
0 |
T2 |
57412 |
1878 |
0 |
0 |
T3 |
562102 |
6400 |
0 |
0 |
T4 |
611441 |
348 |
0 |
0 |
T5 |
481353 |
375 |
0 |
0 |
T6 |
291182 |
1975 |
0 |
0 |
T7 |
11901 |
395 |
0 |
0 |
T8 |
110284 |
7446 |
0 |
0 |
T9 |
120023 |
1060 |
0 |
0 |
T10 |
258340 |
9041 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3451107 |
3357743 |
0 |
0 |
T1 |
41340 |
41217 |
0 |
0 |
T2 |
118 |
20 |
0 |
0 |
T3 |
46840 |
46133 |
0 |
0 |
T4 |
4890 |
4806 |
0 |
0 |
T5 |
3564 |
3513 |
0 |
0 |
T6 |
5881 |
5824 |
0 |
0 |
T7 |
112 |
21 |
0 |
0 |
T8 |
91903 |
91168 |
0 |
0 |
T9 |
3380 |
3327 |
0 |
0 |
T10 |
15656 |
15529 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
2553 |
0 |
0 |
T1 |
496092 |
52 |
0 |
0 |
T2 |
57412 |
1 |
0 |
0 |
T3 |
562102 |
14 |
0 |
0 |
T4 |
611441 |
1 |
0 |
0 |
T5 |
481353 |
1 |
0 |
0 |
T6 |
291182 |
1 |
0 |
0 |
T7 |
11901 |
1 |
0 |
0 |
T8 |
110284 |
18 |
0 |
0 |
T9 |
120023 |
1 |
0 |
0 |
T10 |
258340 |
15 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
774413309 |
773849365 |
0 |
0 |
T1 |
496092 |
495352 |
0 |
0 |
T2 |
57412 |
57341 |
0 |
0 |
T3 |
562102 |
562027 |
0 |
0 |
T4 |
611441 |
611390 |
0 |
0 |
T5 |
481353 |
481299 |
0 |
0 |
T6 |
291182 |
291174 |
0 |
0 |
T7 |
11901 |
11810 |
0 |
0 |
T8 |
110284 |
110277 |
0 |
0 |
T9 |
120023 |
120015 |
0 |
0 |
T10 |
258340 |
257723 |
0 |
0 |