Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	460651	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5695499	1		T1	206		T2	196		T3	235

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1512155	1		T1	62		T2	38		T3	29
values[0x0]	2177044	1		T1	121		T2	128		T3	160
values[0x1]	2466951	1		T1	136		T2	135		T3	162

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203425	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5952725	1		T1	237		T2	212		T3	264

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24548	1		T2	1		T3	4		T6	1034
valid_sources[0x01]	24091	1		T1	1		T3	1		T6	1281
valid_sources[0x02]	24407	1		T1	1		T3	2		T6	1119
valid_sources[0x03]	25936	1		T1	2		T3	1		T6	1135
valid_sources[0x04]	24517	1		T1	1		T6	1199		T13	192
valid_sources[0x05]	23457	1		T2	7		T3	5		T6	1016
valid_sources[0x06]	24800	1		T1	1		T2	2		T3	3
valid_sources[0x07]	24164	1		T1	1		T6	997		T7	2
valid_sources[0x08]	23669	1		T3	2		T6	1032		T7	1
valid_sources[0x09]	25053	1		T1	2		T2	2		T3	2
valid_sources[0x0a]	24993	1		T1	1		T2	3		T3	2
valid_sources[0x0b]	24799	1		T2	1		T6	1120		T7	3
valid_sources[0x0c]	24196	1		T1	1		T3	1		T6	1149
valid_sources[0x0d]	24431	1		T1	2		T6	1178		T7	1
valid_sources[0x0e]	22588	1		T1	1		T3	2		T6	1104
valid_sources[0x0f]	25022	1		T1	1		T2	2		T3	2
valid_sources[0x10]	24037	1		T1	3		T3	1		T6	1206
valid_sources[0x11]	25050	1		T1	1		T2	2		T4	1
valid_sources[0x12]	24342	1		T2	2		T6	1088		T13	291
valid_sources[0x13]	25030	1		T1	1		T3	5		T6	1083
valid_sources[0x14]	23562	1		T1	1		T3	4		T6	1071
valid_sources[0x15]	25689	1		T1	6		T2	4		T6	1168
valid_sources[0x16]	23305	1		T3	1		T6	931		T7	1
valid_sources[0x17]	25135	1		T1	1		T3	2		T6	1175
valid_sources[0x18]	25542	1		T2	2		T3	2		T6	1085
valid_sources[0x19]	25579	1		T1	2		T3	1		T6	1062
valid_sources[0x1a]	21839	1		T1	2		T3	2		T6	1162
valid_sources[0x1b]	22801	1		T1	1		T6	1052		T7	1
valid_sources[0x1c]	24054	1		T1	1		T3	3		T6	1151
valid_sources[0x1d]	23789	1		T2	7		T3	2		T5	5
valid_sources[0x1e]	24564	1		T3	4		T6	1086		T7	1
valid_sources[0x1f]	22789	1		T1	1		T3	1		T6	1039
valid_sources[0x20]	25362	1		T2	1		T6	1181		T7	2
valid_sources[0x21]	23411	1		T1	1		T6	1083		T7	1
valid_sources[0x22]	22837	1		T1	2		T3	2		T6	1074
valid_sources[0x23]	23718	1		T1	1		T3	2		T6	1134
valid_sources[0x24]	25035	1		T1	4		T2	5		T3	2
valid_sources[0x25]	23753	1		T1	1		T2	3		T3	3
valid_sources[0x26]	23483	1		T6	1123		T13	257		T15	888
valid_sources[0x27]	23819	1		T6	1046		T7	1		T13	232
valid_sources[0x28]	22359	1		T1	1		T2	6		T3	1
valid_sources[0x29]	22839	1		T3	3		T6	1189		T7	1
valid_sources[0x2a]	24749	1		T1	3		T6	1119		T7	2
valid_sources[0x2b]	23234	1		T1	2		T3	2		T6	1124
valid_sources[0x2c]	25611	1		T1	1		T3	1		T6	1149
valid_sources[0x2d]	23996	1		T6	1013		T7	3		T9	1
valid_sources[0x2e]	23485	1		T5	1		T6	1096		T13	246
valid_sources[0x2f]	24562	1		T6	1252		T7	3		T9	2
valid_sources[0x30]	25583	1		T1	3		T2	3		T3	1
valid_sources[0x31]	23792	1		T2	4		T3	3		T4	1
valid_sources[0x32]	22112	1		T2	7		T3	4		T6	1130
valid_sources[0x33]	25284	1		T1	3		T3	2		T6	1004
valid_sources[0x34]	23648	1		T2	9		T3	2		T6	1097
valid_sources[0x35]	24363	1		T1	1		T2	2		T3	1
valid_sources[0x36]	24290	1		T1	1		T2	1		T3	2
valid_sources[0x37]	23770	1		T3	4		T6	1187		T7	2
valid_sources[0x38]	24964	1		T1	1		T6	1118		T7	3
valid_sources[0x39]	22052	1		T1	1		T3	2		T6	1177
valid_sources[0x3a]	21909	1		T1	1		T3	2		T6	1270
valid_sources[0x3b]	23872	1		T1	2		T6	1056		T7	1
valid_sources[0x3c]	26163	1		T3	1		T6	1118		T13	241
valid_sources[0x3d]	22964	1		T3	1		T6	961		T7	1
valid_sources[0x3e]	24900	1		T1	3		T3	1		T5	1
valid_sources[0x3f]	23709	1		T1	1		T3	2		T6	1016
valid_sources[0x40]	22178	1		T1	2		T2	7		T3	1
valid_sources[0x41]	25738	1		T3	1		T6	1258		T13	260
valid_sources[0x42]	22570	1		T1	2		T6	1154		T13	249
valid_sources[0x43]	24773	1		T1	1		T2	3		T3	2
valid_sources[0x44]	22686	1		T2	4		T3	1		T6	1051
valid_sources[0x45]	23561	1		T1	2		T3	3		T6	1201
valid_sources[0x46]	24830	1		T1	1		T3	1		T6	1192
valid_sources[0x47]	22006	1		T6	1071		T7	3		T13	250
valid_sources[0x48]	22567	1		T1	1		T3	5		T6	1233
valid_sources[0x49]	24558	1		T1	1		T2	3		T3	2
valid_sources[0x4a]	23872	1		T1	1		T2	2		T3	1
valid_sources[0x4b]	25186	1		T3	5		T6	1015		T13	205
valid_sources[0x4c]	22701	1		T2	3		T6	1115		T13	170
valid_sources[0x4d]	23069	1		T1	2		T3	2		T6	1116
valid_sources[0x4e]	25598	1		T1	1		T3	2		T6	1125
valid_sources[0x4f]	25157	1		T3	4		T6	1238		T7	2
valid_sources[0x50]	23676	1		T3	3		T6	1141		T7	1
valid_sources[0x51]	22916	1		T1	1		T6	1010		T13	318
valid_sources[0x52]	23008	1		T1	4		T3	2		T6	1033
valid_sources[0x53]	22812	1		T1	6		T3	5		T6	1121
valid_sources[0x54]	22774	1		T3	3		T5	1		T6	948
valid_sources[0x55]	23766	1		T1	3		T2	7		T3	1
valid_sources[0x56]	23748	1		T1	1		T2	1		T3	1
valid_sources[0x57]	24261	1		T1	2		T3	1		T6	983
valid_sources[0x58]	23833	1		T1	3		T3	2		T6	1166
valid_sources[0x59]	23143	1		T3	3		T6	1048		T7	1
valid_sources[0x5a]	24292	1		T1	3		T2	3		T5	1
valid_sources[0x5b]	24506	1		T1	1		T2	2		T6	1082
valid_sources[0x5c]	24151	1		T1	1		T3	2		T6	1065
valid_sources[0x5d]	25157	1		T1	2		T3	1		T6	1110
valid_sources[0x5e]	23737	1		T3	1		T6	1080		T7	1
valid_sources[0x5f]	24276	1		T1	1		T6	1049		T7	2
valid_sources[0x60]	23002	1		T1	2		T3	1		T6	1040
valid_sources[0x61]	23907	1		T1	1		T3	2		T6	1130
valid_sources[0x62]	24298	1		T2	6		T3	2		T6	1134
valid_sources[0x63]	23162	1		T1	2		T2	2		T5	1
valid_sources[0x64]	23563	1		T1	3		T2	1		T3	3
valid_sources[0x65]	24305	1		T1	1		T3	2		T6	1177
valid_sources[0x66]	23043	1		T1	1		T3	2		T6	1185
valid_sources[0x67]	26515	1		T1	1		T6	1159		T13	263
valid_sources[0x68]	24255	1		T3	2		T6	1084		T13	280
valid_sources[0x69]	23097	1		T1	3		T2	1		T6	1050
valid_sources[0x6a]	25099	1		T1	2		T3	1		T6	1011
valid_sources[0x6b]	26332	1		T1	3		T2	1		T3	3
valid_sources[0x6c]	24893	1		T1	1		T3	5		T6	1118
valid_sources[0x6d]	23555	1		T3	1		T6	962		T7	1
valid_sources[0x6e]	22818	1		T1	4		T2	4		T3	1
valid_sources[0x6f]	24237	1		T1	2		T3	1		T6	959
valid_sources[0x70]	23398	1		T1	2		T4	1		T6	1087
valid_sources[0x71]	22681	1		T6	979		T7	2		T13	263
valid_sources[0x72]	22345	1		T1	1		T2	5		T3	1
valid_sources[0x73]	22301	1		T2	5		T3	2		T6	1055
valid_sources[0x74]	23821	1		T1	1		T2	6		T3	1
valid_sources[0x75]	23789	1		T6	1013		T7	3		T13	180
valid_sources[0x76]	24208	1		T1	3		T3	2		T6	981
valid_sources[0x77]	25047	1		T6	1101		T13	239		T45	2
valid_sources[0x78]	24780	1		T1	2		T5	1		T6	1058
valid_sources[0x79]	23055	1		T1	1		T3	5		T6	1070
valid_sources[0x7a]	24472	1		T1	3		T3	2		T6	1038
valid_sources[0x7b]	23189	1		T1	2		T3	2		T6	1067
valid_sources[0x7c]	24992	1		T2	4		T3	4		T6	1064
valid_sources[0x7d]	23921	1		T1	1		T3	2		T6	1047
valid_sources[0x7e]	25262	1		T1	1		T2	1		T3	3
valid_sources[0x7f]	24076	1		T1	2		T3	1		T6	1246
valid_sources[0x80]	24148	1		T1	2		T3	1		T6	1088

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1419997

1

T1

34

T2

22

T3

11

values[0x0]

all_enables

biggest_size

2139038

1

T1

83

T2

88

T3

118

values[0x1]

all_enables

biggest_size

2136464

1

T1

89

T2

86

T3

106