Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	821611711	6752539	0	0
wdog_bark_thold_rd_A	821611711	144301	0	0
wdog_bite_thold_rd_A	821611711	126934	0	0
wdog_ctrl_rd_A	821611711	126636	0	0
wdog_regwen_rd_A	821611711	145015	0	0
wkup_ctrl_rd_A	821611711	128880	0	0
wkup_thold_hi_rd_A	821611711	144702	0	0
wkup_thold_lo_rd_A	821611711	127341	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821611711	6752539	0	0
T6	806038	302959	0	0
T7	114342	0	0	0
T8	10764	0	0	0
T9	28792	0	0	0
T10	108456	0	0	0
T11	728189	0	0	0
T12	14930	0	0	0
T13	317234	69813	0	0
T15	0	250725	0	0
T23	0	67917	0	0
T30	13353	0	0	0
T38	0	88510	0	0
T39	0	45509	0	0
T40	0	74613	0	0
T41	0	210328	0	0
T42	0	64502	0	0
T43	0	274186	0	0
T44	48685	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821611711	144301	0	0
T13	317234	6987	0	0
T14	612690	0	0	0
T15	715453	0	0	0
T23	0	3424	0	0
T30	13353	0	0	0
T38	0	9409	0	0
T42	0	6543	0	0
T44	48685	0	0	0
T45	109328	0	0	0
T46	791053	0	0	0
T77	0	22258	0	0
T82	0	5416	0	0
T83	0	4566	0	0
T84	0	4388	0	0
T85	0	11344	0	0
T86	0	9637	0	0
T87	29687	0	0	0
T88	37597	0	0	0
T89	8239	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821611711	126934	0	0
T13	317234	5784	0	0
T14	612690	0	0	0
T15	715453	0	0	0
T23	0	3105	0	0
T30	13353	0	0	0
T38	0	7860	0	0
T42	0	5693	0	0
T44	48685	0	0	0
T45	109328	0	0	0
T46	791053	0	0	0
T77	0	20027	0	0
T82	0	4999	0	0
T83	0	4050	0	0
T84	0	3778	0	0
T85	0	10444	0	0
T86	0	8373	0	0
T87	29687	0	0	0
T88	37597	0	0	0
T89	8239	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821611711	126636	0	0
T13	317234	6077	0	0
T14	612690	0	0	0
T15	715453	0	0	0
T23	0	2976	0	0
T30	13353	0	0	0
T38	0	7633	0	0
T42	0	5928	0	0
T44	48685	0	0	0
T45	109328	0	0	0
T46	791053	0	0	0
T77	0	19804	0	0
T82	0	4883	0	0
T83	0	4173	0	0
T84	0	3924	0	0
T85	0	10096	0	0
T86	0	8860	0	0
T87	29687	0	0	0
T88	37597	0	0	0
T89	8239	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821611711	145015	0	0
T13	317234	6690	0	0
T14	612690	0	0	0
T15	715453	0	0	0
T23	0	3653	0	0
T30	13353	0	0	0
T38	0	8866	0	0
T42	0	6598	0	0
T44	48685	0	0	0
T45	109328	0	0	0
T46	791053	0	0	0
T77	0	22897	0	0
T82	0	5906	0	0
T83	0	4820	0	0
T84	0	4437	0	0
T85	0	10996	0	0
T86	0	9567	0	0
T87	29687	0	0	0
T88	37597	0	0	0
T89	8239	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821611711	128880	0	0
T13	317234	6362	0	0
T14	612690	0	0	0
T15	715453	0	0	0
T23	0	2846	0	0
T30	13353	0	0	0
T38	0	8176	0	0
T42	0	5771	0	0
T44	48685	0	0	0
T45	109328	0	0	0
T46	791053	0	0	0
T77	0	20176	0	0
T82	0	5188	0	0
T83	0	4154	0	0
T84	0	3676	0	0
T85	0	10081	0	0
T86	0	8618	0	0
T87	29687	0	0	0
T88	37597	0	0	0
T89	8239	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821611711	144702	0	0
T13	317234	6574	0	0
T14	612690	0	0	0
T15	715453	0	0	0
T23	0	3513	0	0
T30	13353	0	0	0
T38	0	8878	0	0
T42	0	6672	0	0
T44	48685	0	0	0
T45	109328	0	0	0
T46	791053	0	0	0
T77	0	22973	0	0
T82	0	5965	0	0
T83	0	4727	0	0
T84	0	3939	0	0
T85	0	11442	0	0
T86	0	9992	0	0
T87	29687	0	0	0
T88	37597	0	0	0
T89	8239	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821611711	127341	0	0
T13	317234	6051	0	0
T14	612690	0	0	0
T15	715453	0	0	0
T23	0	3087	0	0
T30	13353	0	0	0
T38	0	7520	0	0
T42	0	5887	0	0
T44	48685	0	0	0
T45	109328	0	0	0
T46	791053	0	0	0
T77	0	20101	0	0
T82	0	5093	0	0
T83	0	4034	0	0
T84	0	3837	0	0
T85	0	9970	0	0
T86	0	8718	0	0
T87	29687	0	0	0
T88	37597	0	0	0
T89	8239	0	0	0