Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	341820	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4163108	1		T1	106807		T2	18		T3	226

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1107466	1		T1	28271		T2	1		T3	34
values[0x0]	1590485	1		T1	41131		T2	5		T3	156
values[0x1]	1806977	1		T1	46660		T2	16		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153304	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4351624	1		T1	111868		T2	18		T3	241

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18030	1		T1	484		T12	75		T15	255
valid_sources[0x01]	17197	1		T1	436		T3	1		T6	1
valid_sources[0x02]	17843	1		T1	426		T12	108		T15	232
valid_sources[0x03]	17013	1		T1	365		T3	3		T6	1
valid_sources[0x04]	18205	1		T1	495		T3	4		T12	80
valid_sources[0x05]	16634	1		T1	499		T12	107		T15	258
valid_sources[0x06]	17843	1		T1	502		T3	6		T12	144
valid_sources[0x07]	18442	1		T1	459		T12	104		T15	213
valid_sources[0x08]	17694	1		T1	560		T3	5		T12	102
valid_sources[0x09]	17957	1		T1	384		T12	87		T15	245
valid_sources[0x0a]	16979	1		T1	452		T3	7		T12	98
valid_sources[0x0b]	17312	1		T1	411		T3	1		T6	1
valid_sources[0x0c]	19912	1		T1	384		T10	1		T11	1
valid_sources[0x0d]	16592	1		T1	400		T3	1		T12	98
valid_sources[0x0e]	18195	1		T1	484		T12	117		T15	245
valid_sources[0x0f]	16637	1		T1	457		T3	1		T12	112
valid_sources[0x10]	17749	1		T1	489		T12	146		T15	232
valid_sources[0x11]	18974	1		T1	449		T6	1		T12	103
valid_sources[0x12]	17108	1		T1	425		T3	4		T12	88
valid_sources[0x13]	18199	1		T1	390		T3	1		T6	2
valid_sources[0x14]	16424	1		T1	434		T12	90		T13	3
valid_sources[0x15]	18428	1		T1	477		T12	74		T30	1
valid_sources[0x16]	17319	1		T1	510		T9	1		T12	83
valid_sources[0x17]	17589	1		T1	432		T3	1		T12	107
valid_sources[0x18]	18012	1		T1	423		T2	3		T12	91
valid_sources[0x19]	18364	1		T1	477		T3	1		T5	19
valid_sources[0x1a]	17832	1		T1	450		T3	1		T12	117
valid_sources[0x1b]	17208	1		T1	377		T3	1		T12	79
valid_sources[0x1c]	18105	1		T1	479		T12	103		T30	1
valid_sources[0x1d]	18204	1		T1	452		T3	9		T12	129
valid_sources[0x1e]	16754	1		T1	477		T3	3		T12	114
valid_sources[0x1f]	19005	1		T1	530		T12	73		T30	1
valid_sources[0x20]	17016	1		T1	421		T3	4		T12	68
valid_sources[0x21]	18604	1		T1	485		T12	104		T15	217
valid_sources[0x22]	18070	1		T1	551		T3	4		T12	84
valid_sources[0x23]	15908	1		T1	408		T12	104		T15	195
valid_sources[0x24]	16963	1		T1	395		T3	5		T12	90
valid_sources[0x25]	18888	1		T1	480		T3	1		T12	94
valid_sources[0x26]	17434	1		T1	464		T12	94		T30	1
valid_sources[0x27]	16900	1		T1	418		T12	77		T15	247
valid_sources[0x28]	17828	1		T1	433		T3	3		T12	86
valid_sources[0x29]	17624	1		T1	400		T12	120		T15	221
valid_sources[0x2a]	16408	1		T1	497		T3	5		T6	2
valid_sources[0x2b]	15955	1		T1	423		T3	1		T12	93
valid_sources[0x2c]	17731	1		T1	443		T3	5		T12	123
valid_sources[0x2d]	18695	1		T1	430		T3	7		T12	78
valid_sources[0x2e]	18314	1		T1	451		T3	1		T12	80
valid_sources[0x2f]	19698	1		T1	527		T3	2		T12	84
valid_sources[0x30]	18013	1		T1	503		T3	4		T12	108
valid_sources[0x31]	17285	1		T1	453		T12	126		T15	253
valid_sources[0x32]	17715	1		T1	394		T12	94		T15	263
valid_sources[0x33]	17839	1		T1	490		T11	2		T12	121
valid_sources[0x34]	16578	1		T1	381		T3	4		T12	131
valid_sources[0x35]	18725	1		T1	434		T12	103		T15	270
valid_sources[0x36]	17659	1		T1	421		T3	6		T12	80
valid_sources[0x37]	18443	1		T1	519		T12	115		T15	269
valid_sources[0x38]	17155	1		T1	479		T3	7		T12	109
valid_sources[0x39]	15955	1		T1	445		T3	2		T6	1
valid_sources[0x3a]	17558	1		T1	456		T3	3		T12	90
valid_sources[0x3b]	17641	1		T1	505		T3	2		T12	77
valid_sources[0x3c]	17431	1		T1	502		T3	3		T8	3
valid_sources[0x3d]	17596	1		T1	432		T3	1		T12	68
valid_sources[0x3e]	17650	1		T1	479		T12	94		T15	237
valid_sources[0x3f]	18877	1		T1	398		T7	1		T12	85
valid_sources[0x40]	17044	1		T1	438		T3	2		T12	107
valid_sources[0x41]	16963	1		T1	460		T12	68		T15	208
valid_sources[0x42]	18190	1		T1	435		T3	2		T12	82
valid_sources[0x43]	18992	1		T1	507		T12	92		T15	239
valid_sources[0x44]	17259	1		T1	546		T3	2		T7	2
valid_sources[0x45]	17491	1		T1	447		T12	91		T15	232
valid_sources[0x46]	19488	1		T1	461		T3	1		T10	2
valid_sources[0x47]	16043	1		T1	447		T3	1		T12	83
valid_sources[0x48]	17323	1		T1	415		T12	82		T15	302
valid_sources[0x49]	17114	1		T1	428		T12	98		T15	263
valid_sources[0x4a]	17624	1		T1	435		T12	90		T15	288
valid_sources[0x4b]	18063	1		T1	453		T12	76		T15	214
valid_sources[0x4c]	18271	1		T1	419		T3	3		T12	116
valid_sources[0x4d]	17563	1		T1	476		T3	1		T12	103
valid_sources[0x4e]	17230	1		T1	465		T12	93		T15	260
valid_sources[0x4f]	16322	1		T1	516		T3	3		T12	98
valid_sources[0x50]	16812	1		T1	476		T3	2		T6	1
valid_sources[0x51]	16700	1		T1	481		T12	81		T13	11
valid_sources[0x52]	16425	1		T1	546		T3	3		T12	103
valid_sources[0x53]	16344	1		T1	423		T11	1		T12	132
valid_sources[0x54]	18057	1		T1	446		T12	72		T15	227
valid_sources[0x55]	17303	1		T1	506		T11	2		T12	122
valid_sources[0x56]	17163	1		T1	499		T3	1		T10	1
valid_sources[0x57]	17526	1		T1	432		T12	99		T15	205
valid_sources[0x58]	17653	1		T1	464		T6	1		T12	94
valid_sources[0x59]	17620	1		T1	375		T3	2		T12	87
valid_sources[0x5a]	17018	1		T1	394		T3	2		T12	92
valid_sources[0x5b]	17700	1		T1	442		T3	3		T12	85
valid_sources[0x5c]	17187	1		T1	515		T12	104		T15	212
valid_sources[0x5d]	16462	1		T1	420		T12	84		T15	214
valid_sources[0x5e]	19144	1		T1	427		T12	100		T15	261
valid_sources[0x5f]	16286	1		T1	493		T3	5		T12	99
valid_sources[0x60]	16879	1		T1	440		T12	96		T15	261
valid_sources[0x61]	17863	1		T1	483		T12	110		T15	207
valid_sources[0x62]	16405	1		T1	422		T3	1		T6	2
valid_sources[0x63]	17658	1		T1	482		T12	93		T30	1
valid_sources[0x64]	17227	1		T1	477		T12	104		T30	1
valid_sources[0x65]	17815	1		T1	425		T3	3		T12	106
valid_sources[0x66]	17692	1		T1	513		T8	5		T10	7
valid_sources[0x67]	15657	1		T1	443		T12	116		T15	222
valid_sources[0x68]	17753	1		T1	396		T12	82		T15	210
valid_sources[0x69]	18139	1		T1	475		T12	102		T15	256
valid_sources[0x6a]	18313	1		T1	545		T3	4		T12	54
valid_sources[0x6b]	17417	1		T1	427		T3	1		T8	1
valid_sources[0x6c]	16844	1		T1	484		T12	97		T15	237
valid_sources[0x6d]	16216	1		T1	428		T6	2		T7	7
valid_sources[0x6e]	17988	1		T1	444		T12	110		T15	202
valid_sources[0x6f]	17093	1		T1	448		T12	62		T15	213
valid_sources[0x70]	17891	1		T1	489		T3	3		T12	113
valid_sources[0x71]	17572	1		T1	478		T3	2		T11	4
valid_sources[0x72]	15681	1		T1	445		T6	1		T12	112
valid_sources[0x73]	18095	1		T1	462		T3	3		T12	112
valid_sources[0x74]	18530	1		T1	446		T3	1		T12	126
valid_sources[0x75]	17714	1		T1	465		T12	90		T15	268
valid_sources[0x76]	17274	1		T1	495		T12	99		T15	216
valid_sources[0x77]	16844	1		T1	550		T11	2		T12	134
valid_sources[0x78]	18820	1		T1	511		T12	123		T15	241
valid_sources[0x79]	17122	1		T1	483		T3	1		T12	103
valid_sources[0x7a]	16316	1		T1	517		T12	97		T15	225
valid_sources[0x7b]	17526	1		T1	420		T12	74		T13	2
valid_sources[0x7c]	18164	1		T1	450		T4	4		T12	101
valid_sources[0x7d]	18458	1		T1	491		T6	1		T12	117
valid_sources[0x7e]	17521	1		T1	532		T3	2		T12	81
valid_sources[0x7f]	17010	1		T1	500		T12	69		T13	4
valid_sources[0x80]	17505	1		T1	427		T12	107		T15	219

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1037768

1

T1

26483

T2

1

T3

18

values[0x0]

all_enables

biggest_size

1561145

1

T1

40294

T2

5

T3

102

values[0x1]

all_enables

biggest_size

1564195

1

T1

40030

T2

12

T3

106