Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	725675202	4898882	0	0
wdog_bark_thold_rd_A	725675202	102952	0	0
wdog_bite_thold_rd_A	725675202	90231	0	0
wdog_ctrl_rd_A	725675202	88935	0	0
wdog_regwen_rd_A	725675202	102644	0	0
wkup_ctrl_rd_A	725675202	88635	0	0
wkup_thold_hi_rd_A	725675202	102482	0	0
wkup_thold_lo_rd_A	725675202	88748	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725675202	4898882	0	0
T1	460618	127216	0	0
T2	20048	0	0	0
T3	687329	0	0	0
T4	35092	0	0	0
T5	55735	0	0	0
T6	11504	0	0	0
T7	245273	0	0	0
T8	515821	0	0	0
T9	160862	0	0	0
T10	40896	0	0	0
T12	0	25180	0	0
T15	0	65701	0	0
T27	0	89123	0	0
T28	0	112517	0	0
T31	0	60236	0	0
T40	0	185964	0	0
T41	0	53030	0	0
T42	0	147579	0	0
T43	0	134564	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725675202	102952	0	0
T12	119384	2547	0	0
T13	103246	0	0	0
T14	310574	0	0	0
T15	248866	0	0	0
T16	743519	0	0	0
T30	51430	0	0	0
T31	349343	2943	0	0
T32	3497	0	0	0
T42	0	15980	0	0
T81	0	6517	0	0
T85	0	14462	0	0
T86	0	9765	0	0
T87	0	7812	0	0
T88	0	22807	0	0
T89	0	2187	0	0
T90	0	8194	0	0
T91	214613	0	0	0
T92	23385	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725675202	90231	0	0
T12	119384	2278	0	0
T13	103246	0	0	0
T14	310574	0	0	0
T15	248866	0	0	0
T16	743519	0	0	0
T30	51430	0	0	0
T31	349343	2721	0	0
T32	3497	0	0	0
T42	0	14055	0	0
T81	0	5542	0	0
T85	0	12723	0	0
T86	0	8436	0	0
T87	0	6713	0	0
T88	0	19894	0	0
T89	0	1932	0	0
T90	0	7076	0	0
T91	214613	0	0	0
T92	23385	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725675202	88935	0	0
T12	119384	2316	0	0
T13	103246	0	0	0
T14	310574	0	0	0
T15	248866	0	0	0
T16	743519	0	0	0
T30	51430	0	0	0
T31	349343	2686	0	0
T32	3497	0	0	0
T42	0	13895	0	0
T81	0	5543	0	0
T85	0	12339	0	0
T86	0	8552	0	0
T87	0	6604	0	0
T88	0	19566	0	0
T89	0	1772	0	0
T90	0	6878	0	0
T91	214613	0	0	0
T92	23385	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725675202	102644	0	0
T12	119384	2499	0	0
T13	103246	0	0	0
T14	310574	0	0	0
T15	248866	0	0	0
T16	743519	0	0	0
T30	51430	0	0	0
T31	349343	2868	0	0
T32	3497	0	0	0
T42	0	15853	0	0
T81	0	6095	0	0
T85	0	14238	0	0
T86	0	10008	0	0
T87	0	7486	0	0
T88	0	23114	0	0
T89	0	2203	0	0
T90	0	8399	0	0
T91	214613	0	0	0
T92	23385	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725675202	88635	0	0
T12	119384	2195	0	0
T13	103246	0	0	0
T14	310574	0	0	0
T15	248866	0	0	0
T16	743519	0	0	0
T30	51430	0	0	0
T31	349343	2736	0	0
T32	3497	0	0	0
T42	0	13368	0	0
T81	0	5256	0	0
T85	0	12796	0	0
T86	0	8312	0	0
T87	0	6294	0	0
T88	0	19806	0	0
T89	0	1940	0	0
T90	0	7064	0	0
T91	214613	0	0	0
T92	23385	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725675202	102482	0	0
T12	119384	2566	0	0
T13	103246	0	0	0
T14	310574	0	0	0
T15	248866	0	0	0
T16	743519	0	0	0
T30	51430	0	0	0
T31	349343	3235	0	0
T32	3497	0	0	0
T42	0	15557	0	0
T81	0	6629	0	0
T85	0	13883	0	0
T86	0	9776	0	0
T87	0	7511	0	0
T88	0	22893	0	0
T89	0	2152	0	0
T90	0	8600	0	0
T91	214613	0	0	0
T92	23385	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725675202	88748	0	0
T12	119384	2173	0	0
T13	103246	0	0	0
T14	310574	0	0	0
T15	248866	0	0	0
T16	743519	0	0	0
T30	51430	0	0	0
T31	349343	2549	0	0
T32	3497	0	0	0
T42	0	13455	0	0
T81	0	5581	0	0
T85	0	12423	0	0
T86	0	8740	0	0
T87	0	6785	0	0
T88	0	19492	0	0
T89	0	1731	0	0
T90	0	7073	0	0
T91	214613	0	0	0
T92	23385	0	0	0