Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	655792069	5842182	0	0
wdog_bark_thold_rd_A	655792069	133465	0	0
wdog_bite_thold_rd_A	655792069	116393	0	0
wdog_ctrl_rd_A	655792069	118800	0	0
wdog_regwen_rd_A	655792069	135417	0	0
wkup_ctrl_rd_A	655792069	116125	0	0
wkup_thold_hi_rd_A	655792069	133360	0	0
wkup_thold_lo_rd_A	655792069	118060	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655792069	5842182	0	0
T1	123482	216941	0	0
T2	128153	0	0	0
T3	18236	0	0	0
T4	139062	0	0	0
T5	122743	0	0	0
T6	14349	0	0	0
T7	103316	337341	0	0
T8	57234	0	0	0
T9	863198	313213	0	0
T10	274126	0	0	0
T14	0	71483	0	0
T25	0	74769	0	0
T26	0	71367	0	0
T31	0	124498	0	0
T32	0	80648	0	0
T39	0	61053	0	0
T40	0	99674	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655792069	133465	0	0
T25	0	7016	0	0
T26	0	7304	0	0
T32	302191	0	0	0
T39	255414	3260	0	0
T40	0	9784	0	0
T41	10454	0	0	0
T42	210587	0	0	0
T47	0	14329	0	0
T92	0	9702	0	0
T93	0	4593	0	0
T94	0	17711	0	0
T95	0	5769	0	0
T96	0	6111	0	0
T97	355567	0	0	0
T98	274819	0	0	0
T99	988508	0	0	0
T100	45210	0	0	0
T101	52560	0	0	0
T102	25783	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655792069	116393	0	0
T25	0	6668	0	0
T26	0	6484	0	0
T32	302191	0	0	0
T39	255414	2812	0	0
T40	0	8680	0	0
T41	10454	0	0	0
T42	210587	0	0	0
T47	0	12404	0	0
T92	0	8660	0	0
T93	0	3716	0	0
T94	0	16197	0	0
T95	0	4710	0	0
T96	0	5463	0	0
T97	355567	0	0	0
T98	274819	0	0	0
T99	988508	0	0	0
T100	45210	0	0	0
T101	52560	0	0	0
T102	25783	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655792069	118800	0	0
T25	0	6596	0	0
T26	0	6913	0	0
T32	302191	0	0	0
T39	255414	2789	0	0
T40	0	8669	0	0
T41	10454	0	0	0
T42	210587	0	0	0
T47	0	12662	0	0
T92	0	8534	0	0
T93	0	4169	0	0
T94	0	16218	0	0
T95	0	4663	0	0
T96	0	5716	0	0
T97	355567	0	0	0
T98	274819	0	0	0
T99	988508	0	0	0
T100	45210	0	0	0
T101	52560	0	0	0
T102	25783	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655792069	135417	0	0
T25	0	7236	0	0
T26	0	7596	0	0
T32	302191	0	0	0
T39	255414	3139	0	0
T40	0	10467	0	0
T41	10454	0	0	0
T42	210587	0	0	0
T47	0	14814	0	0
T92	0	9854	0	0
T93	0	4623	0	0
T94	0	18164	0	0
T95	0	5698	0	0
T96	0	6869	0	0
T97	355567	0	0	0
T98	274819	0	0	0
T99	988508	0	0	0
T100	45210	0	0	0
T101	52560	0	0	0
T102	25783	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655792069	116125	0	0
T25	0	6329	0	0
T26	0	6433	0	0
T32	302191	0	0	0
T39	255414	2821	0	0
T40	0	8534	0	0
T41	10454	0	0	0
T42	210587	0	0	0
T47	0	12619	0	0
T92	0	8634	0	0
T93	0	3951	0	0
T94	0	15662	0	0
T95	0	4684	0	0
T96	0	5515	0	0
T97	355567	0	0	0
T98	274819	0	0	0
T99	988508	0	0	0
T100	45210	0	0	0
T101	52560	0	0	0
T102	25783	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655792069	133360	0	0
T25	0	6915	0	0
T26	0	7298	0	0
T32	302191	0	0	0
T39	255414	2929	0	0
T40	0	9976	0	0
T41	10454	0	0	0
T42	210587	0	0	0
T47	0	14554	0	0
T92	0	9666	0	0
T93	0	4422	0	0
T94	0	18422	0	0
T95	0	5555	0	0
T96	0	6543	0	0
T97	355567	0	0	0
T98	274819	0	0	0
T99	988508	0	0	0
T100	45210	0	0	0
T101	52560	0	0	0
T102	25783	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655792069	118060	0	0
T25	0	6234	0	0
T26	0	6285	0	0
T32	302191	0	0	0
T39	255414	2700	0	0
T40	0	9133	0	0
T41	10454	0	0	0
T42	210587	0	0	0
T47	0	12985	0	0
T92	0	8866	0	0
T93	0	3911	0	0
T94	0	15597	0	0
T95	0	5068	0	0
T96	0	5836	0	0
T97	355567	0	0	0
T98	274819	0	0	0
T99	988508	0	0	0
T100	45210	0	0	0
T101	52560	0	0	0
T102	25783	0	0	0