Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	302949	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3651757	1		T1	13		T2	12		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	970649	1		T1	1		T2	1		T3	1
values[0x0]	1398361	1		T1	9		T2	8		T3	11
values[0x1]	1585696	1		T1	10		T2	10		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	136160	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3818546	1		T1	14		T2	12		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14757	1		T7	383		T10	186		T15	133
valid_sources[0x01]	13879	1		T7	307		T10	196		T15	154
valid_sources[0x02]	15868	1		T7	302		T10	188		T13	1
valid_sources[0x03]	15525	1		T7	265		T10	222		T15	167
valid_sources[0x04]	16019	1		T4	3		T7	359		T10	203
valid_sources[0x05]	16557	1		T4	1		T7	421		T10	234
valid_sources[0x06]	15781	1		T7	157		T10	233		T15	158
valid_sources[0x07]	14875	1		T7	176		T10	226		T15	128
valid_sources[0x08]	15659	1		T5	1		T7	927		T10	224
valid_sources[0x09]	16626	1		T7	112		T10	202		T15	166
valid_sources[0x0a]	15092	1		T7	85		T10	181		T15	169
valid_sources[0x0b]	14354	1		T7	389		T10	245		T15	147
valid_sources[0x0c]	16364	1		T7	458		T10	172		T15	143
valid_sources[0x0d]	15811	1		T7	160		T10	209		T15	155
valid_sources[0x0e]	17288	1		T7	505		T10	184		T13	1
valid_sources[0x0f]	15137	1		T7	524		T10	148		T15	146
valid_sources[0x10]	15524	1		T7	530		T10	214		T15	148
valid_sources[0x11]	15025	1		T7	222		T10	197		T15	160
valid_sources[0x12]	15471	1		T7	216		T10	220		T15	150
valid_sources[0x13]	14591	1		T7	275		T10	190		T15	138
valid_sources[0x14]	14776	1		T7	274		T10	197		T15	156
valid_sources[0x15]	15453	1		T7	414		T10	236		T15	132
valid_sources[0x16]	15057	1		T7	241		T10	198		T23	1
valid_sources[0x17]	14619	1		T7	460		T10	174		T15	143
valid_sources[0x18]	14078	1		T7	35		T10	198		T13	1
valid_sources[0x19]	14761	1		T5	1		T7	371		T10	217
valid_sources[0x1a]	16039	1		T7	108		T10	189		T23	2
valid_sources[0x1b]	15791	1		T7	504		T10	180		T15	163
valid_sources[0x1c]	16307	1		T7	229		T10	194		T15	133
valid_sources[0x1d]	15055	1		T7	495		T10	201		T15	145
valid_sources[0x1e]	14294	1		T7	227		T10	225		T15	135
valid_sources[0x1f]	16195	1		T7	477		T10	216		T15	166
valid_sources[0x20]	14777	1		T7	465		T10	207		T13	1
valid_sources[0x21]	13997	1		T7	47		T10	247		T15	116
valid_sources[0x22]	15121	1		T5	1		T7	337		T10	238
valid_sources[0x23]	15782	1		T7	749		T10	222		T15	120
valid_sources[0x24]	15111	1		T2	1		T7	498		T10	204
valid_sources[0x25]	15825	1		T7	322		T10	223		T11	2
valid_sources[0x26]	15523	1		T4	1		T7	157		T10	133
valid_sources[0x27]	14254	1		T3	2		T7	492		T10	236
valid_sources[0x28]	15355	1		T5	1		T7	325		T10	175
valid_sources[0x29]	15219	1		T7	76		T10	271		T14	1
valid_sources[0x2a]	16216	1		T7	219		T10	199		T15	160
valid_sources[0x2b]	15796	1		T7	211		T10	232		T12	1
valid_sources[0x2c]	15396	1		T7	404		T10	169		T15	142
valid_sources[0x2d]	14643	1		T7	161		T10	259		T15	138
valid_sources[0x2e]	15542	1		T7	66		T10	174		T11	1
valid_sources[0x2f]	15179	1		T7	274		T10	201		T12	1
valid_sources[0x30]	16320	1		T7	660		T10	186		T15	136
valid_sources[0x31]	16728	1		T6	19		T7	443		T10	186
valid_sources[0x32]	14135	1		T7	283		T10	195		T15	138
valid_sources[0x33]	16145	1		T7	205		T10	225		T15	139
valid_sources[0x34]	14607	1		T7	359		T10	211		T15	148
valid_sources[0x35]	15991	1		T7	25		T10	199		T15	159
valid_sources[0x36]	15197	1		T7	348		T10	171		T15	128
valid_sources[0x37]	15694	1		T7	475		T10	203		T15	159
valid_sources[0x38]	16089	1		T2	6		T7	424		T10	222
valid_sources[0x39]	15278	1		T7	188		T10	186		T15	141
valid_sources[0x3a]	15906	1		T7	492		T10	197		T15	156
valid_sources[0x3b]	14891	1		T3	2		T4	2		T7	58
valid_sources[0x3c]	13308	1		T7	90		T10	196		T15	140
valid_sources[0x3d]	16209	1		T7	366		T10	185		T11	1
valid_sources[0x3e]	15996	1		T7	160		T10	201		T15	144
valid_sources[0x3f]	15264	1		T7	277		T10	228		T15	137
valid_sources[0x40]	15011	1		T7	369		T10	213		T15	146
valid_sources[0x41]	16471	1		T7	143		T10	190		T23	1
valid_sources[0x42]	15733	1		T7	205		T10	179		T15	160
valid_sources[0x43]	14330	1		T7	281		T10	223		T15	162
valid_sources[0x44]	14597	1		T7	357		T10	174		T15	128
valid_sources[0x45]	15253	1		T7	59		T10	204		T15	155
valid_sources[0x46]	15254	1		T7	52		T10	237		T15	138
valid_sources[0x47]	15084	1		T7	221		T10	231		T13	1
valid_sources[0x48]	15117	1		T7	169		T10	179		T15	141
valid_sources[0x49]	15975	1		T7	407		T10	230		T15	146
valid_sources[0x4a]	15877	1		T7	336		T10	198		T15	153
valid_sources[0x4b]	16978	1		T5	1		T7	381		T10	233
valid_sources[0x4c]	15712	1		T7	412		T10	183		T15	143
valid_sources[0x4d]	14773	1		T4	1		T7	170		T10	229
valid_sources[0x4e]	15912	1		T7	319		T10	243		T12	1
valid_sources[0x4f]	14854	1		T7	436		T10	225		T15	139
valid_sources[0x50]	15690	1		T7	207		T10	223		T23	2
valid_sources[0x51]	17389	1		T7	445		T10	201		T11	2
valid_sources[0x52]	14333	1		T7	156		T10	221		T15	149
valid_sources[0x53]	15941	1		T7	361		T10	204		T15	155
valid_sources[0x54]	14478	1		T4	1		T7	342		T10	215
valid_sources[0x55]	15839	1		T7	365		T10	184		T15	134
valid_sources[0x56]	15954	1		T7	405		T10	224		T15	147
valid_sources[0x57]	15778	1		T7	207		T10	221		T15	163
valid_sources[0x58]	15488	1		T7	232		T10	226		T15	141
valid_sources[0x59]	15789	1		T7	247		T10	235		T15	138
valid_sources[0x5a]	15075	1		T7	287		T10	227		T12	1
valid_sources[0x5b]	14907	1		T5	1		T7	474		T10	222
valid_sources[0x5c]	15790	1		T7	581		T10	220		T15	164
valid_sources[0x5d]	14629	1		T7	346		T10	211		T15	160
valid_sources[0x5e]	16053	1		T7	558		T10	224		T15	156
valid_sources[0x5f]	14325	1		T7	306		T10	183		T15	119
valid_sources[0x60]	15521	1		T7	213		T10	192		T15	144
valid_sources[0x61]	14941	1		T5	1		T7	336		T10	200
valid_sources[0x62]	16208	1		T4	2		T7	287		T10	170
valid_sources[0x63]	15391	1		T7	467		T10	216		T15	162
valid_sources[0x64]	15083	1		T7	629		T10	239		T14	6
valid_sources[0x65]	14903	1		T7	412		T10	236		T15	160
valid_sources[0x66]	16188	1		T7	606		T10	208		T15	160
valid_sources[0x67]	15663	1		T7	177		T10	227		T15	151
valid_sources[0x68]	15783	1		T7	304		T10	201		T15	151
valid_sources[0x69]	13811	1		T7	261		T10	181		T15	170
valid_sources[0x6a]	14725	1		T7	207		T10	231		T12	1
valid_sources[0x6b]	15068	1		T7	335		T10	252		T11	1
valid_sources[0x6c]	14284	1		T7	226		T10	168		T15	150
valid_sources[0x6d]	16830	1		T7	512		T10	219		T15	130
valid_sources[0x6e]	15727	1		T3	1		T7	218		T10	234
valid_sources[0x6f]	15101	1		T2	3		T7	95		T10	210
valid_sources[0x70]	17174	1		T7	965		T10	197		T15	143
valid_sources[0x71]	14837	1		T7	468		T8	22		T10	191
valid_sources[0x72]	13828	1		T7	159		T10	219		T15	152
valid_sources[0x73]	16653	1		T7	439		T10	209		T13	1
valid_sources[0x74]	14686	1		T7	381		T10	234		T15	138
valid_sources[0x75]	15605	1		T7	150		T10	226		T12	1
valid_sources[0x76]	16696	1		T7	487		T10	182		T15	133
valid_sources[0x77]	15671	1		T7	220		T10	200		T14	3
valid_sources[0x78]	14971	1		T4	1		T7	269		T10	194
valid_sources[0x79]	15612	1		T7	277		T10	233		T12	1
valid_sources[0x7a]	17287	1		T7	278		T10	227		T15	139
valid_sources[0x7b]	16920	1		T7	724		T10	223		T15	143
valid_sources[0x7c]	14105	1		T5	1		T7	204		T10	208
valid_sources[0x7d]	15447	1		T5	2		T7	204		T10	177
valid_sources[0x7e]	13513	1		T7	72		T10	177		T15	138
valid_sources[0x7f]	17184	1		T7	221		T10	197		T13	1
valid_sources[0x80]	16284	1		T7	662		T10	257		T15	115

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

908814

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1371863

1

T1

6

T2

6

T3

10

values[0x1]

all_enables

biggest_size

1371080

1

T1

6

T2

5

T3

4