Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	726802199	4341584	0	0
wdog_bark_thold_rd_A	726802199	171728	0	0
wdog_bite_thold_rd_A	726802199	149037	0	0
wdog_ctrl_rd_A	726802199	150244	0	0
wdog_regwen_rd_A	726802199	171648	0	0
wkup_ctrl_rd_A	726802199	150876	0	0
wkup_thold_hi_rd_A	726802199	169972	0	0
wkup_thold_lo_rd_A	726802199	148838	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726802199	4341584	0	0
T7	384601	80595	0	0
T8	9039	0	0	0
T9	11907	0	0	0
T10	243863	57424	0	0
T11	358348	0	0	0
T12	48066	0	0	0
T13	11235	0	0	0
T14	52595	0	0	0
T15	0	40328	0	0
T23	54550	0	0	0
T26	0	76060	0	0
T27	0	50235	0	0
T28	0	12597	0	0
T35	0	198824	0	0
T42	0	119885	0	0
T43	0	80216	0	0
T44	0	95969	0	0
T45	27701	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726802199	171728	0	0
T7	384601	8190	0	0
T8	9039	0	0	0
T9	11907	0	0	0
T10	243863	5676	0	0
T11	358348	0	0	0
T12	48066	0	0	0
T13	11235	0	0	0
T14	52595	0	0	0
T15	0	3941	0	0
T23	54550	0	0	0
T28	0	1278	0	0
T35	0	18828	0	0
T43	0	8493	0	0
T45	27701	0	0	0
T47	0	9206	0	0
T97	0	4211	0	0
T98	0	11708	0	0
T99	0	9762	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726802199	149037	0	0
T7	384601	7198	0	0
T8	9039	0	0	0
T9	11907	0	0	0
T10	243863	5140	0	0
T11	358348	0	0	0
T12	48066	0	0	0
T13	11235	0	0	0
T14	52595	0	0	0
T15	0	3517	0	0
T23	54550	0	0	0
T28	0	1125	0	0
T35	0	16429	0	0
T43	0	7139	0	0
T45	27701	0	0	0
T47	0	8264	0	0
T97	0	3546	0	0
T98	0	10399	0	0
T99	0	8300	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726802199	150244	0	0
T7	384601	7164	0	0
T8	9039	0	0	0
T9	11907	0	0	0
T10	243863	4874	0	0
T11	358348	0	0	0
T12	48066	0	0	0
T13	11235	0	0	0
T14	52595	0	0	0
T15	0	3535	0	0
T23	54550	0	0	0
T28	0	1125	0	0
T35	0	16633	0	0
T43	0	7513	0	0
T45	27701	0	0	0
T47	0	8019	0	0
T97	0	3835	0	0
T98	0	10321	0	0
T99	0	8630	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726802199	171648	0	0
T7	384601	8406	0	0
T8	9039	0	0	0
T9	11907	0	0	0
T10	243863	5443	0	0
T11	358348	0	0	0
T12	48066	0	0	0
T13	11235	0	0	0
T14	52595	0	0	0
T15	0	3933	0	0
T23	54550	0	0	0
T28	0	1331	0	0
T35	0	18977	0	0
T43	0	8157	0	0
T45	27701	0	0	0
T47	0	8903	0	0
T97	0	4420	0	0
T98	0	11759	0	0
T99	0	9589	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726802199	150876	0	0
T7	384601	6981	0	0
T8	9039	0	0	0
T9	11907	0	0	0
T10	243863	4890	0	0
T11	358348	0	0	0
T12	48066	0	0	0
T13	11235	0	0	0
T14	52595	0	0	0
T15	0	3564	0	0
T23	54550	0	0	0
T28	0	1164	0	0
T35	0	16268	0	0
T43	0	7234	0	0
T45	27701	0	0	0
T47	0	8272	0	0
T97	0	3606	0	0
T98	0	9940	0	0
T99	0	8831	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726802199	169972	0	0
T7	384601	7926	0	0
T8	9039	0	0	0
T9	11907	0	0	0
T10	243863	5837	0	0
T11	358348	0	0	0
T12	48066	0	0	0
T13	11235	0	0	0
T14	52595	0	0	0
T15	0	4013	0	0
T23	54550	0	0	0
T28	0	1417	0	0
T35	0	18324	0	0
T43	0	8116	0	0
T45	27701	0	0	0
T47	0	9190	0	0
T97	0	4007	0	0
T98	0	12244	0	0
T99	0	9611	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726802199	148838	0	0
T7	384601	7039	0	0
T8	9039	0	0	0
T9	11907	0	0	0
T10	243863	4855	0	0
T11	358348	0	0	0
T12	48066	0	0	0
T13	11235	0	0	0
T14	52595	0	0	0
T15	0	3626	0	0
T23	54550	0	0	0
T28	0	1116	0	0
T35	0	16164	0	0
T43	0	7387	0	0
T45	27701	0	0	0
T47	0	8323	0	0
T97	0	3485	0	0
T98	0	10700	0	0
T99	0	8426	0	0